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--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" INDATA_ACLR_A="NONE" NUMWORDS_A=128 NUMWORDS_B=128 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=7 WIDTHAD_B=7 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_a q_b wren_a
--VERSION_BEGIN 4.2 cbx_altsyncram 2004:11:16:15:31:02:SJ cbx_cycloneii 2004:08:25:19:39:42:SJ cbx_lpm_add_sub 2004:10:25:10:56:48:SJ cbx_lpm_compare 2004:10:18:11:29:46:SJ cbx_lpm_decode 2004:08:15:21:16:20:SJ cbx_lpm_mux 2004:08:15:21:16:24:SJ cbx_mgl 2004:10:26:10:32:18:SJ cbx_stratix 2004:09:23:18:28:34:SJ cbx_stratixii 2004:08:10:15:01:36:SJ cbx_util_mgl 2004:09:29:16:04:00:SJ  VERSION_END


--  Copyright (C) 1988-2002 Altera Corporation
--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
--  support information,  device programming or simulation file,  and any other
--  associated  documentation or information  provided by  Altera  or a partner
--  under  Altera's   Megafunction   Partnership   Program  may  be  used  only
--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--  other  use  of such  megafunction  design,  netlist,  support  information,
--  device programming or simulation file,  or any other  related documentation
--  or information  is prohibited  for  any  other purpose,  including, but not
--  limited to  modification,  reverse engineering,  de-compiling, or use  with
--  any other  silicon devices,  unless such use is  explicitly  licensed under
--  a separate agreement with  Altera  or a megafunction partner.  Title to the
--  intellectual property,  including patents,  copyrights,  trademarks,  trade
--  secrets,  or maskworks,  embodied in any such megafunction design, netlist,
--  support  information,  device programming or simulation file,  or any other
--  related documentation or information provided by  Altera  or a megafunction
--  partner, remains with Altera, the megafunction partner, or their respective
--  licensors. No other licenses, including any licenses needed under any third
--  party's intellectual property, are provided herein.


PARAMETERS
(
        PORT_A_ADDRESS_WIDTH = 1,
        PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
        PORT_A_DATA_WIDTH = 1,
        PORT_B_ADDRESS_WIDTH = 1,
        PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
        PORT_B_DATA_WIDTH = 1
);
FUNCTION cyclone_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe)
WITH (  CONNECTIVITY_CHECKING,  DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS,  INIT_FILE,      INIT_FILE_LAYOUT,       LOGICAL_RAM_NAME,       mem_init0,      mem_init1,      MIXED_PORT_FEED_THROUGH_MODE,   OPERATION_MODE, PORT_A_ADDRESS_CLEAR,   PORT_A_ADDRESS_WIDTH,   PORT_A_BYTE_ENABLE_CLEAR,       PORT_A_BYTE_ENABLE_MASK_WIDTH,  PORT_A_DATA_IN_CLEAR,   PORT_A_DATA_OUT_CLEAR,  PORT_A_DATA_OUT_CLOCK,  PORT_A_DATA_WIDTH,      PORT_A_FIRST_ADDRESS,   PORT_A_FIRST_BIT_NUMBER,        PORT_A_LAST_ADDRESS,    PORT_A_LOGICAL_RAM_DEPTH,       PORT_A_LOGICAL_RAM_WIDTH,       PORT_A_WRITE_ENABLE_CLEAR,      PORT_B_ADDRESS_CLEAR,   PORT_B_ADDRESS_CLOCK,   PORT_B_ADDRESS_WIDTH,   PORT_B_BYTE_ENABLE_CLEAR,       PORT_B_BYTE_ENABLE_CLOCK,       PORT_B_BYTE_ENABLE_MASK_WIDTH,  PORT_B_DATA_IN_CLEAR,   PORT_B_DATA_IN_CLOCK,   PORT_B_DATA_OUT_CLEAR,  PORT_B_DATA_OUT_CLOCK,  PORT_B_DATA_WIDTH,      PORT_B_FIRST_ADDRESS,   PORT_B_FIRST_BIT_NUMBER,        PORT_B_LAST_ADDRESS,    PORT_B_LOGICAL_RAM_DEPTH,       PORT_B_LOGICAL_RAM_WIDTH,       PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR,  PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK,  POWER_UP_UNINITIALIZED,        RAM_BLOCK_TYPE) 
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);

--synthesis_resources = M4K 1 
SUBDESIGN altsyncram_hg91
( 
        address_a[6..0] :       input;
        address_b[6..0] :       input;
        clock0  :       input;
        data_a[7..0]    :       input;
        q_a[7..0]       :       output;
        q_b[7..0]       :       output;
        wren_a  :       input;
) 
VARIABLE 
        ram_block1a0 : cyclone_ram_block
                WITH (
                        CONNECTIVITY_CHECKING = "OFF",
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
                        OPERATION_MODE = "dual_port",
                        PORT_A_ADDRESS_CLEAR = "none",
                        PORT_A_ADDRESS_WIDTH = 7,
                        PORT_A_DATA_IN_CLEAR = "none",
                        PORT_A_DATA_WIDTH = 1,
                        PORT_A_FIRST_ADDRESS = 0,
                        PORT_A_FIRST_BIT_NUMBER = 0,
                        PORT_A_LAST_ADDRESS = 127,
                        PORT_A_LOGICAL_RAM_DEPTH = 128,
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
                        PORT_A_WRITE_ENABLE_CLEAR = "none",
                        PORT_B_ADDRESS_CLEAR = "none",
                        PORT_B_ADDRESS_CLOCK = "clock0",
                        PORT_B_ADDRESS_WIDTH = 7,
                        PORT_B_DATA_WIDTH = 1,
                        PORT_B_FIRST_ADDRESS = 0,
                        PORT_B_FIRST_BIT_NUMBER = 0,
                        PORT_B_LAST_ADDRESS = 127,
                        PORT_B_LOGICAL_RAM_DEPTH = 128,
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
                        RAM_BLOCK_TYPE = "auto"
                );
        ram_block1a1 : cyclone_ram_block
                WITH (
                        CONNECTIVITY_CHECKING = "OFF",
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
                        OPERATION_MODE = "dual_port",
                        PORT_A_ADDRESS_CLEAR = "none",
                        PORT_A_ADDRESS_WIDTH = 7,
                        PORT_A_DATA_IN_CLEAR = "none",
                        PORT_A_DATA_WIDTH = 1,
                        PORT_A_FIRST_ADDRESS = 0,
                        PORT_A_FIRST_BIT_NUMBER = 1,
                        PORT_A_LAST_ADDRESS = 127,
                        PORT_A_LOGICAL_RAM_DEPTH = 128,
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
                        PORT_A_WRITE_ENABLE_CLEAR = "none",
                        PORT_B_ADDRESS_CLEAR = "none",
                        PORT_B_ADDRESS_CLOCK = "clock0",
                        PORT_B_ADDRESS_WIDTH = 7,
                        PORT_B_DATA_WIDTH = 1,
                        PORT_B_FIRST_ADDRESS = 0,
                        PORT_B_FIRST_BIT_NUMBER = 1,
                        PORT_B_LAST_ADDRESS = 127,
                        PORT_B_LOGICAL_RAM_DEPTH = 128,
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
                        RAM_BLOCK_TYPE = "auto"
                );
        ram_block1a2 : cyclone_ram_block
                WITH (
                        CONNECTIVITY_CHECKING = "OFF",
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
                        OPERATION_MODE = "dual_port",
                        PORT_A_ADDRESS_CLEAR = "none",
                        PORT_A_ADDRESS_WIDTH = 7,
                        PORT_A_DATA_IN_CLEAR = "none",
                        PORT_A_DATA_WIDTH = 1,
                        PORT_A_FIRST_ADDRESS = 0,
                        PORT_A_FIRST_BIT_NUMBER = 2,
                        PORT_A_LAST_ADDRESS = 127,
                        PORT_A_LOGICAL_RAM_DEPTH = 128,
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
                        PORT_A_WRITE_ENABLE_CLEAR = "none",
                        PORT_B_ADDRESS_CLEAR = "none",
                        PORT_B_ADDRESS_CLOCK = "clock0",
                        PORT_B_ADDRESS_WIDTH = 7,
                        PORT_B_DATA_WIDTH = 1,
                        PORT_B_FIRST_ADDRESS = 0,
                        PORT_B_FIRST_BIT_NUMBER = 2,
                        PORT_B_LAST_ADDRESS = 127,
                        PORT_B_LOGICAL_RAM_DEPTH = 128,
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
                        RAM_BLOCK_TYPE = "auto"
                );
        ram_block1a3 : cyclone_ram_block
                WITH (
                        CONNECTIVITY_CHECKING = "OFF",
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
                        OPERATION_MODE = "dual_port",
                        PORT_A_ADDRESS_CLEAR = "none",
                        PORT_A_ADDRESS_WIDTH = 7,
                        PORT_A_DATA_IN_CLEAR = "none",
                        PORT_A_DATA_WIDTH = 1,
                        PORT_A_FIRST_ADDRESS = 0,
                        PORT_A_FIRST_BIT_NUMBER = 3,
                        PORT_A_LAST_ADDRESS = 127,
                        PORT_A_LOGICAL_RAM_DEPTH = 128,
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
                        PORT_A_WRITE_ENABLE_CLEAR = "none",
                        PORT_B_ADDRESS_CLEAR = "none",
                        PORT_B_ADDRESS_CLOCK = "clock0",
                        PORT_B_ADDRESS_WIDTH = 7,
                        PORT_B_DATA_WIDTH = 1,
                        PORT_B_FIRST_ADDRESS = 0,
                        PORT_B_FIRST_BIT_NUMBER = 3,
                        PORT_B_LAST_ADDRESS = 127,
                        PORT_B_LOGICAL_RAM_DEPTH = 128,
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
                        RAM_BLOCK_TYPE = "auto"
                );
        ram_block1a4 : cyclone_ram_block
                WITH (
                        CONNECTIVITY_CHECKING = "OFF",
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
                        OPERATION_MODE = "dual_port",
                        PORT_A_ADDRESS_CLEAR = "none",
                        PORT_A_ADDRESS_WIDTH = 7,
                        PORT_A_DATA_IN_CLEAR = "none",
                        PORT_A_DATA_WIDTH = 1,
                        PORT_A_FIRST_ADDRESS = 0,
                        PORT_A_FIRST_BIT_NUMBER = 4,
                        PORT_A_LAST_ADDRESS = 127,
                        PORT_A_LOGICAL_RAM_DEPTH = 128,
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
                        PORT_A_WRITE_ENABLE_CLEAR = "none",
                        PORT_B_ADDRESS_CLEAR = "none",
                        PORT_B_ADDRESS_CLOCK = "clock0",
                        PORT_B_ADDRESS_WIDTH = 7,
                        PORT_B_DATA_WIDTH = 1,
                        PORT_B_FIRST_ADDRESS = 0,
                        PORT_B_FIRST_BIT_NUMBER = 4,
                        PORT_B_LAST_ADDRESS = 127,
                        PORT_B_LOGICAL_RAM_DEPTH = 128,
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
                        RAM_BLOCK_TYPE = "auto"
                );
        ram_block1a5 : cyclone_ram_block
                WITH (
                        CONNECTIVITY_CHECKING = "OFF",
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
                        OPERATION_MODE = "dual_port",
                        PORT_A_ADDRESS_CLEAR = "none",
                        PORT_A_ADDRESS_WIDTH = 7,
                        PORT_A_DATA_IN_CLEAR = "none",
                        PORT_A_DATA_WIDTH = 1,
                        PORT_A_FIRST_ADDRESS = 0,
                        PORT_A_FIRST_BIT_NUMBER = 5,
                        PORT_A_LAST_ADDRESS = 127,
                        PORT_A_LOGICAL_RAM_DEPTH = 128,
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
                        PORT_A_WRITE_ENABLE_CLEAR = "none",
                        PORT_B_ADDRESS_CLEAR = "none",
                        PORT_B_ADDRESS_CLOCK = "clock0",
                        PORT_B_ADDRESS_WIDTH = 7,
                        PORT_B_DATA_WIDTH = 1,
                        PORT_B_FIRST_ADDRESS = 0,
                        PORT_B_FIRST_BIT_NUMBER = 5,
                        PORT_B_LAST_ADDRESS = 127,
                        PORT_B_LOGICAL_RAM_DEPTH = 128,
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
                        RAM_BLOCK_TYPE = "auto"
                );
        ram_block1a6 : cyclone_ram_block
                WITH (
                        CONNECTIVITY_CHECKING = "OFF",
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
                        OPERATION_MODE = "dual_port",
                        PORT_A_ADDRESS_CLEAR = "none",
                        PORT_A_ADDRESS_WIDTH = 7,
                        PORT_A_DATA_IN_CLEAR = "none",
                        PORT_A_DATA_WIDTH = 1,
                        PORT_A_FIRST_ADDRESS = 0,
                        PORT_A_FIRST_BIT_NUMBER = 6,
                        PORT_A_LAST_ADDRESS = 127,
                        PORT_A_LOGICAL_RAM_DEPTH = 128,
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
                        PORT_A_WRITE_ENABLE_CLEAR = "none",
                        PORT_B_ADDRESS_CLEAR = "none",
                        PORT_B_ADDRESS_CLOCK = "clock0",
                        PORT_B_ADDRESS_WIDTH = 7,
                        PORT_B_DATA_WIDTH = 1,
                        PORT_B_FIRST_ADDRESS = 0,
                        PORT_B_FIRST_BIT_NUMBER = 6,
                        PORT_B_LAST_ADDRESS = 127,
                        PORT_B_LOGICAL_RAM_DEPTH = 128,
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
                        RAM_BLOCK_TYPE = "auto"
                );
        ram_block1a7 : cyclone_ram_block
                WITH (
                        CONNECTIVITY_CHECKING = "OFF",
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
                        OPERATION_MODE = "dual_port",
                        PORT_A_ADDRESS_CLEAR = "none",
                        PORT_A_ADDRESS_WIDTH = 7,
                        PORT_A_DATA_IN_CLEAR = "none",
                        PORT_A_DATA_WIDTH = 1,
                        PORT_A_FIRST_ADDRESS = 0,
                        PORT_A_FIRST_BIT_NUMBER = 7,
                        PORT_A_LAST_ADDRESS = 127,
                        PORT_A_LOGICAL_RAM_DEPTH = 128,
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
                        PORT_A_WRITE_ENABLE_CLEAR = "none",
                        PORT_B_ADDRESS_CLEAR = "none",
                        PORT_B_ADDRESS_CLOCK = "clock0",
                        PORT_B_ADDRESS_WIDTH = 7,
                        PORT_B_DATA_WIDTH = 1,
                        PORT_B_FIRST_ADDRESS = 0,
                        PORT_B_FIRST_BIT_NUMBER = 7,
                        PORT_B_LAST_ADDRESS = 127,
                        PORT_B_LOGICAL_RAM_DEPTH = 128,
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
                        RAM_BLOCK_TYPE = "auto"
                );
        address_a_wire[6..0]    : WIRE;
        address_b_wire[6..0]    : WIRE;

BEGIN 
        ram_block1a[7..0].clk0 = clock0;
        ram_block1a[0].portaaddr[] = ( address_a_wire[6..0]);
        ram_block1a[1].portaaddr[] = ( address_a_wire[6..0]);
        ram_block1a[2].portaaddr[] = ( address_a_wire[6..0]);
        ram_block1a[3].portaaddr[] = ( address_a_wire[6..0]);
        ram_block1a[4].portaaddr[] = ( address_a_wire[6..0]);
        ram_block1a[5].portaaddr[] = ( address_a_wire[6..0]);
        ram_block1a[6].portaaddr[] = ( address_a_wire[6..0]);
        ram_block1a[7].portaaddr[] = ( address_a_wire[6..0]);
        ram_block1a[0].portadatain[] = ( data_a[0..0]);
        ram_block1a[1].portadatain[] = ( data_a[1..1]);
        ram_block1a[2].portadatain[] = ( data_a[2..2]);
        ram_block1a[3].portadatain[] = ( data_a[3..3]);
        ram_block1a[4].portadatain[] = ( data_a[4..4]);
        ram_block1a[5].portadatain[] = ( data_a[5..5]);
        ram_block1a[6].portadatain[] = ( data_a[6..6]);
        ram_block1a[7].portadatain[] = ( data_a[7..7]);
        ram_block1a[7..0].portawe = wren_a;
        ram_block1a[0].portbaddr[] = ( address_b_wire[6..0]);
        ram_block1a[1].portbaddr[] = ( address_b_wire[6..0]);
        ram_block1a[2].portbaddr[] = ( address_b_wire[6..0]);
        ram_block1a[3].portbaddr[] = ( address_b_wire[6..0]);
        ram_block1a[4].portbaddr[] = ( address_b_wire[6..0]);
        ram_block1a[5].portbaddr[] = ( address_b_wire[6..0]);
        ram_block1a[6].portbaddr[] = ( address_b_wire[6..0]);
        ram_block1a[7].portbaddr[] = ( address_b_wire[6..0]);
        ram_block1a[0].portbrewe = B"1";
        ram_block1a[1].portbrewe = B"1";
        ram_block1a[2].portbrewe = B"1";
        ram_block1a[3].portbrewe = B"1";
        ram_block1a[4].portbrewe = B"1";
        ram_block1a[5].portbrewe = B"1";
        ram_block1a[6].portbrewe = B"1";
        ram_block1a[7].portbrewe = B"1";
        address_a_wire[] = address_a[];
        address_b_wire[] = address_b[];
        q_b[] = ( ram_block1a[7].portbdataout[0..0], ram_block1a[6].portbdataout[0..0], ram_block1a[5].portbdataout[0..0], ram_block1a[4].portbdataout[0..0], ram_block1a[3].portbdataout[0..0], ram_block1a[2].portbdataout[0..0], ram_block1a[1].portbdataout[0..0], ram_block1a[0].portbdataout[0..0]);
END;
--VALID FILE