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[/] [lwrisc/] [trunk/] [RTL/] [altera/] [rom32x12.v] - Rev 19
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// megafunction wizard: %ROM: 1-PORT% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altsyncram // ============================================================ // File Name: rom32x12.v // Megafunction Name(s): // altsyncram // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 4.2 Build 157 12/07/2004 SJ Full Version // ************************************************************ //Copyright (C) 1991-2004 Altera Corporation //Any megafunction design, and related netlist (encrypted or decrypted), //support information, device programming or simulation file, and any other //associated documentation or information provided by Altera or a partner //under Altera's Megafunction Partnership Program may be used only //to program PLD devices (but not masked PLD devices) from Altera. Any //other use of such megafunction design, netlist, support information, //device programming or simulation file, or any other related documentation //or information is prohibited for any other purpose, including, but not //limited to modification, reverse engineering, de-compiling, or use with //any other silicon devices, unless such use is explicitly licensed under //a separate agreement with Altera or a megafunction partner. Title to the //intellectual property, including patents, copyrights, trademarks, trade //secrets, or maskworks, embodied in any such megafunction design, netlist, //support information, device programming or simulation file, or any other //related documentation or information provided by Altera or a megafunction //partner, remains with Altera, the megafunction partner, or their respective //licensors. No other licenses, including any licenses needed under any third //party's intellectual property, are provided herein. // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module rom32x12 ( address, clock, q); input [4:0] address; input clock; output [7:0] q; wire [7:0] sub_wire0; wire [7:0] q = sub_wire0[7:0]; altsyncram altsyncram_component ( .clock0 (clock), .address_a (address), .q_a (sub_wire0) // synopsys translate_off , .aclr0 (), .aclr1 (), .address_b (), .addressstall_a (), .addressstall_b (), .byteena_a (), .byteena_b (), .clock1 (), .clocken0 (), .clocken1 (), .data_a (), .data_b (), .q_b (), .rden_b (), .wren_a (), .wren_b () // synopsys translate_on ); defparam altsyncram_component.intended_device_family = "Cyclone", altsyncram_component.width_a = 8, altsyncram_component.widthad_a = 5, altsyncram_component.numwords_a = 32, altsyncram_component.operation_mode = "ROM", altsyncram_component.outdata_reg_a = "UNREGISTERED", altsyncram_component.address_aclr_a = "NONE", altsyncram_component.outdata_aclr_a = "NONE", altsyncram_component.width_byteena_a = 1, altsyncram_component.init_file = "init_file.mif", altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", altsyncram_component.lpm_type = "altsyncram"; endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: WidthData NUMERIC "8" // Retrieval info: PRIVATE: WidthAddr NUMERIC "5" // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32" // Retrieval info: PRIVATE: SingleClock NUMERIC "1" // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" // Retrieval info: PRIVATE: RegAddr NUMERIC "1" // Retrieval info: PRIVATE: RegOutput NUMERIC "0" // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" // Retrieval info: PRIVATE: AclrByte NUMERIC "0" // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" // Retrieval info: PRIVATE: Clken NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" // Retrieval info: PRIVATE: MIFfilename STRING "init_file.mif" // Retrieval info: PRIVATE: UseLCs NUMERIC "0" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5" // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32" // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" // Retrieval info: CONSTANT: INIT_FILE STRING "init_file.mif" // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" // Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL address[4..0] // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock // Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0 // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: GEN_FILE: TYPE_NORMAL rom32x12.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL rom32x12.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL rom32x12.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL rom32x12.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL rom32x12_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL rom32x12_bb.v FALSE