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<html> <body><samp><pre> <!@TC:1205142074> #Program: Synplify Pro 8.1 #OS: Windows_NT <a name=compilerReport13>$ Start of Compile #Mon Mar 10 17:41:12 2008 Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005 Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved @I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera.v" @I::"C:\Program Files\Synplicity\fpga_81\lib\altera\cyclone.v" @I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera_mf.v" @I::"C:\Program Files\Synplicity\fpga_81\lib\altera\altera_lpm.v" @I::"D:\LWRISC\RTL\sim_rom.v" @I::"D:\LWRISC\RTL\test.v" @I::"D:\LWRISC\RTL\mem_man.v" @I:"D:\LWRISC\RTL\mem_man.v":"D:\LWRISC\RTL\clairisc_def.h" @I::"D:\LWRISC\RTL\memory.v" @I:"D:\LWRISC\RTL\memory.v":"D:\LWRISC\RTL\clairisc_def.h" @I:"D:\LWRISC\RTL\memory.v":"D:\LWRISC\RTL\rom_set.h" @I::"D:\LWRISC\RTL\risc_core.v" @I:"D:\LWRISC\RTL\risc_core.v":"D:\LWRISC\RTL\clairisc_def.h" @I::"D:\LWRISC\RTL\altera\rom512x12.v" @N: : <a href="d:\lwrisc\rtl\altera\rom512x12.v:39:12:39:25:@N::@XP_MSG">rom512x12.v(39)</a><!@TM:1205142084> | Read directive translate_off @N: : <a href="d:\lwrisc\rtl\altera\rom512x12.v:41:12:41:24:@N::@XP_MSG">rom512x12.v(41)</a><!@TM:1205142084> | Read directive translate_on @N: : <a href="d:\lwrisc\rtl\altera\rom512x12.v:58:16:58:29:@N::@XP_MSG">rom512x12.v(58)</a><!@TM:1205142084> | Read directive translate_off @N: : <a href="d:\lwrisc\rtl\altera\rom512x12.v:76:16:76:28:@N::@XP_MSG">rom512x12.v(76)</a><!@TM:1205142084> | Read directive translate_on @I::"D:\LWRISC\RTL\altera\rom1024x12.v" @N: : <a href="d:\lwrisc\rtl\altera\rom1024x12.v:39:12:39:25:@N::@XP_MSG">rom1024x12.v(39)</a><!@TM:1205142084> | Read directive translate_off @N: : <a href="d:\lwrisc\rtl\altera\rom1024x12.v:41:12:41:24:@N::@XP_MSG">rom1024x12.v(41)</a><!@TM:1205142084> | Read directive translate_on @N: : <a href="d:\lwrisc\rtl\altera\rom1024x12.v:58:16:58:29:@N::@XP_MSG">rom1024x12.v(58)</a><!@TM:1205142084> | Read directive translate_off @N: : <a href="d:\lwrisc\rtl\altera\rom1024x12.v:76:16:76:28:@N::@XP_MSG">rom1024x12.v(76)</a><!@TM:1205142084> | Read directive translate_on @I::"D:\LWRISC\RTL\altera\rom2048x12.v" @N: : <a href="d:\lwrisc\rtl\altera\rom2048x12.v:39:12:39:25:@N::@XP_MSG">rom2048x12.v(39)</a><!@TM:1205142084> | Read directive translate_off @N: : <a href="d:\lwrisc\rtl\altera\rom2048x12.v:41:12:41:24:@N::@XP_MSG">rom2048x12.v(41)</a><!@TM:1205142084> | Read directive translate_on @N: : <a href="d:\lwrisc\rtl\altera\rom2048x12.v:58:16:58:29:@N::@XP_MSG">rom2048x12.v(58)</a><!@TM:1205142084> | Read directive translate_off @N: : <a href="d:\lwrisc\rtl\altera\rom2048x12.v:76:16:76:28:@N::@XP_MSG">rom2048x12.v(76)</a><!@TM:1205142084> | Read directive translate_on @I::"D:\LWRISC\RTL\altera\ram128x8.v" @N: : <a href="d:\lwrisc\rtl\altera\ram128x8.v:141:12:141:25:@N::@XP_MSG">ram128x8.v(141)</a><!@TM:1205142084> | Read directive translate_off @N: : <a href="d:\lwrisc\rtl\altera\ram128x8.v:143:12:143:24:@N::@XP_MSG">ram128x8.v(143)</a><!@TM:1205142084> | Read directive translate_on @N: : <a href="d:\lwrisc\rtl\altera\ram128x8.v:169:31:169:44:@N::@XP_MSG">ram128x8.v(169)</a><!@TM:1205142084> | Read directive translate_off @N: : <a href="d:\lwrisc\rtl\altera\ram128x8.v:184:31:184:43:@N::@XP_MSG">ram128x8.v(184)</a><!@TM:1205142084> | Read directive translate_on @I::"D:\LWRISC\RTL\altera\rom32x12.v" @N: : <a href="d:\lwrisc\rtl\altera\rom32x12.v:39:12:39:25:@N::@XP_MSG">rom32x12.v(39)</a><!@TM:1205142084> | Read directive translate_off @N: : <a href="d:\lwrisc\rtl\altera\rom32x12.v:41:12:41:24:@N::@XP_MSG">rom32x12.v(41)</a><!@TM:1205142084> | Read directive translate_on @N: : <a href="d:\lwrisc\rtl\altera\rom32x12.v:58:16:58:29:@N::@XP_MSG">rom32x12.v(58)</a><!@TM:1205142084> | Read directive translate_off @N: : <a href="d:\lwrisc\rtl\altera\rom32x12.v:76:16:76:28:@N::@XP_MSG">rom32x12.v(76)</a><!@TM:1205142084> | Read directive translate_on @I::"D:\LWRISC\RTL\altera\rom64x12.v" @N: : <a href="d:\lwrisc\rtl\altera\rom64x12.v:39:12:39:25:@N::@XP_MSG">rom64x12.v(39)</a><!@TM:1205142084> | Read directive translate_off @N: : <a href="d:\lwrisc\rtl\altera\rom64x12.v:41:12:41:24:@N::@XP_MSG">rom64x12.v(41)</a><!@TM:1205142084> | Read directive translate_on @N: : <a href="d:\lwrisc\rtl\altera\rom64x12.v:58:16:58:29:@N::@XP_MSG">rom64x12.v(58)</a><!@TM:1205142084> | Read directive translate_off @N: : <a href="d:\lwrisc\rtl\altera\rom64x12.v:76:16:76:28:@N::@XP_MSG">rom64x12.v(76)</a><!@TM:1205142084> | Read directive translate_on @I::"D:\LWRISC\RTL\altera\rom128x12.v" @N: : <a href="d:\lwrisc\rtl\altera\rom128x12.v:39:12:39:25:@N::@XP_MSG">rom128x12.v(39)</a><!@TM:1205142084> | Read directive translate_off @N: : <a href="d:\lwrisc\rtl\altera\rom128x12.v:41:12:41:24:@N::@XP_MSG">rom128x12.v(41)</a><!@TM:1205142084> | Read directive translate_on @N: : <a href="d:\lwrisc\rtl\altera\rom128x12.v:58:16:58:29:@N::@XP_MSG">rom128x12.v(58)</a><!@TM:1205142084> | Read directive translate_off @N: : <a href="d:\lwrisc\rtl\altera\rom128x12.v:76:16:76:28:@N::@XP_MSG">rom128x12.v(76)</a><!@TM:1205142084> | Read directive translate_on @I::"D:\LWRISC\RTL\altera\rom256x12.v" @N: : <a href="d:\lwrisc\rtl\altera\rom256x12.v:39:12:39:25:@N::@XP_MSG">rom256x12.v(39)</a><!@TM:1205142084> | Read directive translate_off @N: : <a href="d:\lwrisc\rtl\altera\rom256x12.v:41:12:41:24:@N::@XP_MSG">rom256x12.v(41)</a><!@TM:1205142084> | Read directive translate_on @N: : <a href="d:\lwrisc\rtl\altera\rom256x12.v:58:16:58:29:@N::@XP_MSG">rom256x12.v(58)</a><!@TM:1205142084> | Read directive translate_off @N: : <a href="d:\lwrisc\rtl\altera\rom256x12.v:76:16:76:28:@N::@XP_MSG">rom256x12.v(76)</a><!@TM:1205142084> | Read directive translate_on Verilog syntax check successful! File D:\LWRISC\RTL\sim_rom.v changed - recompiling