Subversion Repositories lwrisc

#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2005 Synplicity, Inc.
# All rights reserved
#

# Set logfile options
vif_set_result_file  ClaiRISC_core.vlf

# Set technology for TCL script
vif_set_technology -architecture FPGA -vendor Altera

# RTL and technology files
vif_add_library -original $env(QUARTUS_ROOTDIR)/eda/fv_lib/verilog
vif_add_file -original -verilog ../../RTL/sim_rom.v
vif_add_file -original -verilog ../../RTL/test.v
vif_add_file -original -verilog ../../RTL/mem_man.v
vif_add_file -original -verilog ../../RTL/memory.v
vif_add_file -original -verilog ../../RTL/risc_core.v
vif_add_file -original -verilog ../../RTL/altera/rom512x12.v
vif_add_file -original -verilog ../../RTL/altera/rom1024x12.v
vif_add_file -original -verilog ../../RTL/altera/rom2048x12.v
vif_add_file -original -verilog ../../RTL/altera/ram128x8.v
vif_add_file -original -verilog ../../RTL/altera/rom32x12.v
vif_add_file -original -verilog ../../RTL/altera/rom64x12.v
vif_add_file -original -verilog ../../RTL/altera/rom128x12.v
vif_add_file -original -verilog ../../RTL/altera/rom256x12.v
vif_set_top_module -original -top ClaiRISC_core
 
vif_add_library -translated $env(QUARTUS_ROOTDIR)/eda/fv_lib/verilog
vif_add_file -translated -verilog ClaiRISC_core.vqm
vif_set_top_module -translated -top ClaiRISC_core 
# Read FSM encoding

# Memory map points

# SRL map points

# Compiler constant registers

# Compiler constant latches

# Compiler RTL sequential redundancies

# RTL sequential redundancies
vif_set_merge -original  w_c_wr_r w_alu_op_r[1]
vif_set_merge -original  w_alu_op_r[3] w_alu_op_r[2]
vif_set_merge -original  w_ek_r[0] mem_man/rd_addr_r[0]
vif_set_merge -original  w_ek_r[0] w_wbadd_r[0]
vif_set_merge -original  w_ek_r[1] mem_man/rd_addr_r[1]
vif_set_merge -original  w_ek_r[1] w_wbadd_r[1]
vif_set_merge -original  w_ek_r[2] mem_man/rd_addr_r[2]
vif_set_merge -original  w_ek_r[2] w_wbadd_r[2]
vif_set_merge -original  w_ek_r[3] mem_man/rd_addr_r[3]
vif_set_merge -original  w_ek_r[3] w_wbadd_r[3]
vif_set_merge -original  w_ek_r[4] mem_man/rd_addr_r[4]
vif_set_merge -original  w_ek_r[4] w_wbadd_r[4]

# Technology sequential redundancies

# Inversion map points

# Port mappping and directions

# Black box mapping
vif_set_black_box altsyncram

vif_set_map_point -blackbox -original mem_man/i_reg_file/altsyncram_component -translated mem_man/i_reg_file/altsyncram_component
vif_set_map_point -blackbox -original program_rom/i_alt_ram/altsyncram_component -translated program_rom/i_alt_ram/altsyncram_component

# Other sequential cells, including multidimensional arrays

# Constant Registers
vif_set_constant -original -1 mem_man/wr_addr_r[6]
vif_set_constant -original -1 mem_man/rd_addr_r[6]
vif_set_constant -original -1 mem_man/wr_addr_r[5]
vif_set_constant -original -1 mem_man/rd_addr_r[5]
vif_set_constant -original 1 w_reg_muxb_r

# Retimed Registers
vif_set_sequential_verify -retimed -register -original mem_man/status[0] -translated mem_man/status_0__Z
vif_set_sequential_verify -retimed -register -original mem_man/status[1] -translated mem_man/status_1__Z
vif_set_sequential_verify -retimed -register -original mem_man/status[2] -translated mem_man/status_2__Z
vif_set_sequential_verify -retimed -register -original mem_man/status[3] -translated mem_man/status_3__Z
vif_set_sequential_verify -retimed -register -original mem_man/status[4] -translated mem_man/status_4__Z
vif_set_sequential_verify -retimed -register -original mem_man/status[5] -translated mem_man/status_5__Z
vif_set_sequential_verify -retimed -register -original mem_man/status[6] -translated mem_man/status_6__Z
vif_set_sequential_verify -retimed -register -original mem_man/status[7] -translated mem_man/status_7__Z
vif_set_sequential_verify -retimed -register -original mem_man/reg_in0[0] -translated mem_man/reg_in0_0__Z
vif_set_sequential_verify -retimed -register -original mem_man/reg_in0[1] -translated mem_man/reg_in0_1__Z
vif_set_sequential_verify -retimed -register -original mem_man/reg_in0[2] -translated mem_man/reg_in0_2__Z
vif_set_sequential_verify -retimed -register -original mem_man/reg_in0[3] -translated mem_man/reg_in0_3__Z
vif_set_sequential_verify -retimed -register -original mem_man/reg_in0[4] -translated mem_man/reg_in0_4__Z
vif_set_sequential_verify -retimed -register -original mem_man/reg_in0[5] -translated mem_man/reg_in0_5__Z
vif_set_sequential_verify -retimed -register -original mem_man/reg_in0[6] -translated mem_man/reg_in0_6__Z
vif_set_sequential_verify -retimed -register -original mem_man/reg_in0[7] -translated mem_man/reg_in0_7__Z
vif_set_sequential_verify -retimed -register -original mem_man/wr_addr_r[0] -translated mem_man/wr_addr_r_0__Z
vif_set_sequential_verify -retimed -register -original mem_man/wr_addr_r[4] -translated mem_man/wr_addr_r_4__Z
vif_set_sequential_verify -retimed -register -original mem_man/din_r[0] -translated mem_man/din_r_0__Z
vif_set_sequential_verify -retimed -register -original mem_man/din_r[1] -translated mem_man/din_r_1__Z
vif_set_sequential_verify -retimed -register -original mem_man/din_r[2] -translated mem_man/din_r_2__Z
vif_set_sequential_verify -retimed -register -original mem_man/din_r[3] -translated mem_man/din_r_3__Z
vif_set_sequential_verify -retimed -register -original mem_man/din_r[4] -translated mem_man/din_r_4__Z
vif_set_sequential_verify -retimed -register -original mem_man/din_r[5] -translated mem_man/din_r_5__Z
vif_set_sequential_verify -retimed -register -original mem_man/din_r[6] -translated mem_man/din_r_6__Z
vif_set_sequential_verify -retimed -register -original mem_man/wr_addr_r[3] -translated mem_man/wr_addr_r_3__Z
vif_set_sequential_verify -retimed -register -original mem_man/wr_addr_r[2] -translated mem_man/wr_addr_r_2__Z
vif_set_sequential_verify -retimed -register -original mem_man/wr_addr_r[1] -translated mem_man/wr_addr_r_1__Z
vif_set_sequential_verify -retimed -register -original mem_man/reg_in1[7] -translated mem_man/reg_in1_7__Z
vif_set_sequential_verify -retimed -register -original mem_man/reg_in1[6] -translated mem_man/reg_in1_6__Z
vif_set_sequential_verify -retimed -register -original mem_man/reg_in1[5] -translated mem_man/reg_in1_5__Z
vif_set_sequential_verify -retimed -register -original mem_man/reg_in1[4] -translated mem_man/reg_in1_4__Z
vif_set_sequential_verify -retimed -register -original mem_man/reg_in1[3] -translated mem_man/reg_in1_3__Z
vif_set_sequential_verify -retimed -register -original mem_man/reg_in1[2] -translated mem_man/reg_in1_2__Z
vif_set_sequential_verify -retimed -register -original mem_man/reg_in1[1] -translated mem_man/reg_in1_1__Z
vif_set_sequential_verify -retimed -register -original mem_man/reg_in1[0] -translated mem_man/reg_in1_0__Z
vif_set_sequential_verify -retimed -register -original mem_man/wr_en_r -translated mem_man/wr_en_r_Z
vif_set_sequential_verify -retimed -register -original w_w_wr_r -translated w_w_wr_r_Z
vif_set_sequential_verify -retimed -register -original w_c_wr_r -translated w_c_wr_r_Z
vif_set_sequential_verify -retimed -register -original w_mem_wr_r -translated w_mem_wr_r_Z
vif_set_sequential_verify -retimed -register -original w_z_wr_r -translated w_z_wr_r_Z
vif_set_sequential_verify -retimed -register -original w_alu_op_r[0] -translated w_alu_op_r_0__Z
vif_set_sequential_verify -retimed -register -original w_alu_op_r[3] -translated w_alu_op_r_3__Z
vif_set_sequential_verify -retimed -register -original w_alu_op_r[4] -translated w_alu_op_r_4__Z
vif_set_sequential_verify -retimed -register -original w_wreg[0] -translated w_wreg_0__Z
vif_set_sequential_verify -retimed -register -original w_wreg[1] -translated w_wreg_1__Z
vif_set_sequential_verify -retimed -register -original w_wreg[2] -translated w_wreg_2__Z
vif_set_sequential_verify -retimed -register -original w_wreg[3] -translated w_wreg_3__Z
vif_set_sequential_verify -retimed -register -original w_wreg[4] -translated w_wreg_4__Z
vif_set_sequential_verify -retimed -register -original w_wreg[5] -translated w_wreg_5__Z
vif_set_sequential_verify -retimed -register -original w_wreg[6] -translated w_wreg_6__Z
vif_set_sequential_verify -retimed -register -original w_wreg[7] -translated w_wreg_7__Z
vif_set_sequential_verify -retimed -register -original w_ek_r[0] -translated w_ek_r_0__Z
vif_set_sequential_verify -retimed -register -original w_ek_r[1] -translated w_ek_r_1__Z
vif_set_sequential_verify -retimed -register -original w_ek_r[2] -translated w_ek_r_2__Z
vif_set_sequential_verify -retimed -register -original w_ek_r[3] -translated w_ek_r_3__Z
vif_set_sequential_verify -retimed -register -original w_ek_r[4] -translated w_ek_r_4__Z
vif_set_sequential_verify -retimed -register -original w_pc[0] -translated w_pc_0__Z
vif_set_sequential_verify -retimed -register -original w_pc[1] -translated w_pc_1__Z
vif_set_sequential_verify -retimed -register -original w_pc[2] -translated w_pc_2__Z
vif_set_sequential_verify -retimed -register -original w_pc[3] -translated w_pc_3__Z
vif_set_sequential_verify -retimed -register -original w_pc[4] -translated w_pc_4__Z
vif_set_sequential_verify -retimed -register -original w_pc[5] -translated w_pc_5__Z
vif_set_sequential_verify -retimed -register -original w_pc[6] -translated w_pc_6__Z

# Altera MAC annotations