Subversion Repositories m16c5x

NET "Clk" TNM_NET = Clk;
#
#TIMESPEC TS_Clk = PERIOD "Clk" 18.432 ns HIGH 50%;      #  54.2534 MHz 3S50A-4
TIMESPEC TS_Clk = PERIOD "Clk" 16.666 ns HIGH 50%;      #  60.0000 MHz 3S50A-4
#
#TIMESPEC TS_Clk = PERIOD "Clk" 15.000 ns HIGH 50%;      #  66.6666 MHz 3S50A-5
#
NET "Clk_UART" TNM_NET = Clk_UART;
#
TIMESPEC TS_Clk_UART = PERIOD "Clk_UART" 10.000 ns HIGH 50%; # 100.0000 MHz
#
NET "SPI_SCK" TNM_NET = SPI_SCK;
#
TIMESPEC TS_SPI_SCK = PERIOD "SPI_SCK" 15.000 ns HIGH 50%;  #  66.6666 MHz
#
NET "nMCLR"     LOC = P82 | IOSTANDARD = "LVCMOS33" | PULLUP ;
NET "ClkIn"     LOC = P88 | IOSTANDARD = "LVCMOS33" ;
#NET "Clk_UART"  LOC = P9  | IOSTANDARD = "LVCMOS33" ;
#
NET "nWDTE"     LOC = P99 | IOSTANDARD = "LVCMOS33" | PULLUP ;
NET "PROM_WE"   LOC = P39 | IOSTANDARD = "LVCMOS33" | PULLDOWN ;
#
NET "nT0CKI"    LOC = P7  | IOSTANDARD = "LVCMOS33" ;
#
#NET "nCS<0>"    LOC = P20 | IOSTANDARD = "LVCMOS33" ;
#NET "nCS<1>"    LOC = P19 | IOSTANDARD = "LVCMOS33" ;
#NET "nCS<2>"    LOC = P27 | IOSTANDARD = "LVCMOS33" ;
NET "nCS<0>"    LOC = P10 | IOSTANDARD = "LVCMOS33" ;
NET "nCS<1>"    LOC = P12 | IOSTANDARD = "LVCMOS33" ;
NET "nCS<2>"    LOC = P13 | IOSTANDARD = "LVCMOS33" ;
#
NET "SCK"       LOC = P53 | IOSTANDARD = "LVCMOS33" ;
NET "MOSI"      LOC = P46 | IOSTANDARD = "LVCMOS33" ;
NET "MISO"      LOC = P51 | IOSTANDARD = "LVCMOS33" | PULLUP ;
#
NET "TD"        LOC = P90 | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" ;
NET "nRTS"      LOC = P94 | IOSTANDARD = "LVCMOS33" ;
NET "RD"        LOC = P93 | IOSTANDARD = "LVCMOS33" | PULLUP ;
NET "nCTS"      LOC = P98 | IOSTANDARD = "LVCMOS33" | PULLUP ;
NET "DE"        LOC = P89 | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" ;
#
# Test Signals
#
NET "nCSO<0>"    LOC = P20 | IOSTANDARD = "LVCMOS33" ;
NET "nCSO<1>"    LOC = P19 | IOSTANDARD = "LVCMOS33" ;
NET "nCSO<2>"    LOC = P27 | IOSTANDARD = "LVCMOS33" ;
NET "nWait"      LOC = P48 | IOSTANDARD = "LVCMOS33" ;