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#@ ##@ # Running dc_shell Version 2001.08 -- Aug 22, 2001#@ # Date: Tue Jan 15 21:02:25 2008#@source /usr/synopsys/synthesis/admin/setup/.synopsys_dc.setup#@ ##@ ##@ # ".synopsys_dc.setup" Initialization File for#@ ##@ # Dc_Shell and Design_Analyzer#@ ##@ # The variables in this file define the behavior of many parts#@ # of the Synopsys Synthesis Tools. Upon installation, they should#@ # be reviewed and modified to fit your site's needs. Each engineer#@ # can have a .synopsys file in his/her home directory or current#@ # directory to override variable settings in this file.#@ ##@ # Each logical grouping of variables is commented as to their#@ # nature and effect on the Synthesis Commands. Examples of#@ # variable groups are the Compile Variable Group, which affects#@ # the designs produced by the COMPILE command, and the Schematic#@ # Variable Group, which affects the output of the create_schematic#@ # command.#@ ##@ # You can type "man <group_name>_variables" in dc_shell or#@ # design_analyzer to get help about a group of variables.#@ # For instance, to get help about the "system" variable group,#@ # type "help system_variables". You can also type#@ # "man <variable name>", to get help on the that variable's#@ # group.#@ ##@#@ # System variables#@ set sh_command_abbrev_mode "Anywhere"#@ set sh_continue_on_error "true"#@ set sh_enable_page_mode "true"#@ set sh_source_uses_search_path "true"#@ if { [string compare $dc_shell_mode "tcl"] == 0 } {#@ set sh_command_log_file "./command.log"#@ }#@#@#@#@ # Enable debug output on fatal#@ if { $sh_arch == "sparc" || $sh_arch == "sparcOS5" || $sh_arch == "hp700" || $sh_arch == "hpux10" || $sh_arch == "linux" } {#@ setenv SYNOPSYS_TRACE ""#@ }#@#@ ##@ # Load the procedures which make up part of the user interface.#@ ##@ if { [string compare $dc_shell_mode "tcl"] == 0 } {#@ source $synopsys_root/auxx/syn/.dc_common_procs.tcl#@ source $synopsys_root/auxx/syn/.dc_procs.tcl#@ alias list_commands help#@ }#@ ###############################################################################@ ##@ ##@ # FILE: auxx/syn/.dc_common_procs.tcl#@ ##@ # ABSTRACT: These procedures are part of the PrimeTime and DC#@ # user interface.#@ # They are loaded by .synopsys_pt.setup and .synopsys_dc.setup.#@ ##@ ###############################################################################@ ##@ ##@#@#@ ###############################################################################@ ##@ ##@ # PROCEDURE: group_variable#@ ##@ # ABSTRACT: Add a variable to the specified variable group.#@ # This command is typically used by the system#@ # administrator only.#@ ##@ # Below the proc is the command which creates the command#@ # help information and semantic data for the argument.#@ ##@ # RETURNS: 1 if it is successful.#@ # error code if the variable does not exist.#@ # error code of the variable is already in the group.#@ ##@ # SYNTAX: group_variable group_name variable_name#@ ##@ ###############################################################################@ ##@#@#@ proc group_variable { args } {#@ global _Variable_Groups#@#@ parse_proc_arguments -args $args resarr#@ set group $resarr(group)#@ set var $resarr(variable_name)#@#@ if { ![info exists _Variable_Groups($group)] } {#@ set _Variable_Groups($group) ""#@ }#@#@ # Verify that var exists as a global variable#@#@ set cmd "uplevel #0 \{info exists $var\}"#@ if { ![eval $cmd] } {#@ return -code error "Variable '$var' is not defined."#@ }#@#@ # Only add it if it's not already there#@#@ if { [lsearch $_Variable_Groups($group) $var] == -1 } {#@ lappend _Variable_Groups($group) $var#@ }#@#@ return 1#@ }#@#@ define_proc_attributes group_variable -info "Add a variable to a variable group" -command_group "Builtins" -permanent -dont_abbrev -define_args {#@ {group "Variable group name" group}#@ {variable_name "Variable name" variable_name}}#@#@ ###############################################################################@ ##@ ##@ # PROCEDURE: print_variable_group#@ ##@ # ABSTRACT: Shows variables and their values defined in the given group.#@#@ ##@ # Below the proc is the command which creates the command#@ # help information and semantic data for the argument.#@ ##@ # RETURNS: 1 if it is successful.#@ # error code of the variable group does not exist.#@ ##@ # SYNTAX: print_variable_group group_name#@ ##@ ###############################################################################@ ##@#@ proc print_variable_group { args } {#@ global _Variable_Groups#@#@ parse_proc_arguments -args $args resarr#@ set group $resarr(group)#@#@ if { [string compare $group "all"] == 0 } {#@ set cmd "uplevel #0 \{printvar\}"#@ return [eval $cmd]#@ }#@#@ if { ![info exists _Variable_Groups($group)] } {#@ return -code error "Variable group '$group' does not exist."#@ }#@#@ # Print out each global variable in the list. To be totally bulletproof,#@ # test that each variable in the group is still defined. If not, remove#@ # it from the list.#@#@ foreach var [lsort $_Variable_Groups($group)] {#@ set cmd "uplevel #0 \{info exists $var\}"#@ if { ![eval $cmd] } {#@ # Remove it#@ set n [lsearch $_Variable_Groups($group) $var]#@ set $_Variable_Groups($group) [lreplace $_Variable_Groups($group) $n $n]#@ } else {#@ # Print it.#@ set cmd "uplevel #0 \{set $var\}"#@ set val [eval $cmd]#@ echo [format "%-25s = \"%s\"" $var $val]#@ }#@ }#@#@ return 1#@ }#@#@ define_proc_attributes print_variable_group -info "Print the contents of a variable group" -command_group "Builtins" -permanent -define_args {{group "Variable group name" group}}#@#@#@#@ ###############################################################################@ ##@ ##@ # PROCEDURE: _Variable_Groups_Get_Groups#@ ##@ # ABSTRACT: Return a list of all variable groups. This command is hidden#@ # and is used by Design Vision.#@ ##@ # RETURNS: Tcl list of all variable groups including group all#@ ##@ # SYNTAX: _Variable_Groups_Get_Groups#@ ###############################################################################@ ##@#@ proc _Variable_Groups_Get_Groups { } {#@ global _Variable_Groups#@#@ set groups [array names _Variable_Groups]#@ append groups " all"#@ return $groups#@ }#@ define_proc_attributes _Variable_Groups_Get_Groups -hidden#@#@#@ ###############################################################################@ ##@ ##@ # PROCEDURE: _Variable_Groups_Get_Variables_Of_Group#@ ##@ # ABSTRACT: Return a list of all variables of a variable group.#@ # It also works for pseudo group all.#@ ##@ # RETURNS: Tcl list of all variables of a variable group including#@ # pseudo group all#@ ##@ # SYNTAX: _Variable_Groups_Get_Groups#@ ###############################################################################@ ##@#@ proc _Variable_Groups_Get_Variables_Of_Group { group } {#@ global _Variable_Groups#@#@ if { [string compare $group "all"] == 0 } {#@ set itr [array startsearch _Variable_Groups]#@ for { } { [array anymore _Variable_Groups $itr]} { } {#@ set index [array nextelement _Variable_Groups $itr]#@ append vars $_Variable_Groups($index)#@ }#@ array donesearch _Variable_Groups $itr#@ return $vars#@ }#@#@ if { ![info exists _Variable_Groups($group)] } {#@ return -code error "Variable group '$group' does not exist."#@ }#@#@ # Test if all variables in the list of variables are still defined.#@ # Remove not existing variables.#@ foreach var [lsort $_Variable_Groups($group)] {#@ set cmd "uplevel #0 \{info exists $var\}"#@ if { ![eval $cmd] } {#@ # Remove it#@ set n [lsearch $_Variable_Groups($group) $var]#@ set $_Variable_Groups($group) [lreplace $_Variable_Groups($group) $n $n]#@ }#@ }#@ return $_Variable_Groups($group)#@ }#@ define_proc_attributes _Variable_Groups_Get_Variables_Of_Group -hidden#@#@ # -- End source /usr/synopsys/synthesis/auxx/syn/.dc_common_procs.tcl#@ ###############################################################################@ ##@ ##@ # FILE: auxx/syn/.dc_procs.tcl#@ ##@ # ABSTRACT: These procedures are part of the Design Compiler Tcl#@ # user interface.#@ # They are loaded by .synopsys_dc.setup.#@ ##@ ###############################################################################@ ##@ ##@#@ ###############################################################################@ ##@ ##@ # PROCEDURE: read_verilog#@ ##@ # ABSTRACT: Emulate PT's read_verilog command in DC:#@ ##@ # Usage: read_verilog # Read one or more verilog files#@ # *[-hdl_compiler] (Use HDL Compiler (ignored))#@ # file_names (Files to read)#@ ##@ # Modified: Bharat 11/17/99. Use uplevel to ensure that the command#@ # sees user/hidden variables from the top level. Star 92970.#@ ##@ ###############################################################################@ ##@#@ proc read_verilog { args } {#@ parse_proc_arguments -args $args ra#@#@ set cmd [format {read_file -format verilog [list %s]} $ra(file_names)]#@ return [uplevel #0 $cmd]#@ }#@#@ define_proc_attributes read_verilog -info " Read one or more verilog files" -permanent -define_args {#@ {file_names "Files to read" file_names list required}#@ {-hdl_compiler "Use HDL Compiler (ignored)" "" boolean {hidden optional}}#@ }#@#@#@ ###############################################################################@ ##@ ##@ # PROCEDURE: read_vhdl#@ ##@ # ABSTRACT: Emulate PT's read_vhdl command in DC:#@ ##@ # Usage: read_vhdl # Read one or more vhdl files#@ # file_names (Files to read)#@ ##@ ##@ ###############################################################################@ ##@#@ proc read_vhdl { args } {#@ parse_proc_arguments -args $args ra#@#@ set cmd [format {read_file -format vhdl [list %s]} $ra(file_names)]#@ return [uplevel #0 $cmd]#@ }#@#@ define_proc_attributes read_vhdl -info " Read one or more vhdl files" -permanent -define_args {#@ {file_names "Files to read" file_names list required}}#@#@ ###############################################################################@ ##@ ##@ # PROCEDURE: read_db#@ ##@ # ABSTRACT: Emulate PT's read_db command in DC:#@ ##@ # Usage:#@ # read_db # Read one or more db files#@ # *[-netlist_only] (Do not read any attributes from db (ignored))#@ # *[-library] (File is a library DB (ignored))#@ # file_names (Files to read)#@ ##@ ##@ ###############################################################################@ ##@#@ proc read_db { args } {#@ parse_proc_arguments -args $args ra#@#@ set cmd [format {read_file -format db [list %s]} $ra(file_names)]#@ return [uplevel #0 $cmd]#@ }#@#@ define_proc_attributes read_db -info " Read one or more db files" -permanent -define_args {#@ {file_names "Files to read" file_names list required}#@ {-netlist_only "Do not read any attributes from db (ignored)" "" boolean {hidden optional}}#@ {-library "File is a library DB (ignored)" "" boolean {hidden optional}}#@ }#@#@ ###############################################################################@ ##@ ##@ # PROCEDURE: read_edif#@ ##@ # ABSTRACT: Emulate PT's read_edif command in DC:#@ ##@ # Usage:#@ # read_edif # Read one or more edif files#@ # *[-complete_language] (Use ptxr to read the file (ignored))#@ # file_names (Files to read)#@ ##@ ##@ ###############################################################################@ ##@ proc read_edif { args } {#@ parse_proc_arguments -args $args ra#@#@ set cmd [format {read_file -format edif [list %s]} $ra(file_names)]#@ return [uplevel #0 $cmd]#@ }#@#@ define_proc_attributes read_edif -info " Read one or more edif files" -permanent -define_args {#@ {file_names "Files to read" file_names list required}#@ {-complete_language "Use ptxr to read the file (ignored)" "" boolean {hidden optional}}#@ }#@#@ # -- End source /usr/synopsys/synthesis/auxx/syn/.dc_procs.tcl#@#@ # Temporary fix for the LMC_HOME variable- set it to an empty string#@#@ if { [catch {getenv LMC_HOME } __err ] != 0 } {#@ setenv LMC_HOME ""#@ }#@#@#@ ##@ ##@ # Site-Specific Variables#@ ##@ # These are the variables that are most commonly changed at a#@ # specific site, either upon installation of the Synopsys software,#@ # or by specific engineers in their local .synopsys files.#@ ##@ ##@#@ # from the System Variable Group#@ set link_force_case "check_reference"#@ set link_library { * umce13h210t3_tc_120V_25C.db }#@ set physical_library ""#@#@ set search_path [list . ${synopsys_root}/libraries/syn ${synopsys_root}/dw/sim_ver /usr/synopsys/libraries/umc/]#@ set target_library umce13h210t3_tc_120V_25C.db#@ set synthetic_library ""#@ set command_log_file "./command.log"#@ set designer ""#@ set company ""#@ set find_converts_name_lists "false"#@#@ set symbol_library umce13h210t3.sdb#@#@ # from the Schematic Variable Group#@#@ # from the Plot Variable Group#@ if { $sh_arch == "hp700" } {#@ set plot_command "lp -d"#@ } else {#@ set plot_command "lpr -Plw"#@ }#@#@ set view_command_log_file "./view_command.log"#@#@ # from the View Variable group#@ if { $sh_arch == "hp700" } {#@ set text_print_command "lp -d"#@ } else {#@ set text_print_command "lpr -Plw"#@ }#@ ##@ # System Variable Group:#@ ##@ # These variables are system-wide variables.#@ ##@ set arch_init_path ${synopsys_root}/${sh_arch}/motif/syn/uid#@ set auto_link_disable "false"#@ set auto_link_options "-all"#@ set uniquify_naming_style "%s_%d"#@ set verbose_messages "true"#@ set echo_include_commands "true"#@ set preserve_subshells "hdl_shell_exec"#@ set suppress_errors {PWR-18 OPT-932 OPT-317}#@ set change_names_update_inst_tree "true"#@ set change_names_dont_change_bus_members false#@ set default_name_rules ""#@#@ ##@ # Compile Variable Group:#@ ##@ # These variables affect the designs created by the COMPILE command.#@ ##@ set compile_assume_fully_decoded_three_state_busses "false"#@ set compile_automatic_clock_phase_inference "strict"#@ set compile_no_new_cells_at_top_level "false"#@ set compile_dont_touch_annotated_cell_during_inplace_opt "false"#@ set compile_update_annotated_delays_during_inplace_opt "true"#@ set compile_instance_name_prefix "U"#@ set compile_instance_name_suffix ""#@ set compile_negative_logic_methodology "false"#@ set compile_disable_hierarchical_inverter_opt "false"#@ set compile_use_fast_delay_mode "true"#@ set compile_use_low_timing_effort "false"#@ set compile_new_boolean_structure "false"#@ set compile_fix_cell_degradation "false"#@ set compile_preserve_subdesign_interfaces "false"#@ set compile_sequential_area_recovery "false"#@ set port_complement_naming_style "%s_BAR"#@ set compile_implementation_selection "true"#@ set compile_mux_no_boundary_optimization "false"#@ set compile_create_mux_op_hierarchy "true"#@ set compile_delete_unloaded_sequential_cells "true"#@ set reoptimize_design_changed_list_file_name ""#@ set compile_checkpoint_filename "./CHECKPOINT.db"#@ set compile_checkpoint_cpu_interval 0.0#@ set compile_checkpoint_phases "false"#@ set compile_checkpoint_pre_delay_filename "./CHECKPOINT_PRE_DELAY.db"#@ set compile_checkpoint_pre_drc1_filename "./CHECKPOINT_PRE_DRC1.db"#@ set compile_checkpoint_pre_drc2_filename "./CHECKPOINT_PRE_DRC2.db"#@ set compile_checkpoint_pre_area_filename "./CHECKPOINT_PRE_AREA.db"#@ set compile_cpu_limit 0.0#@ set compile_log_format " %elap_time %area %wns %tns %drc %endpoint";#@ set compile_top_all_paths "false"#@ set default_port_connection_class "universal"#@ set compile_dw_simple_mode "false"#@ set compile_simple_mode_block_effort "none"#@ set compile_hold_reduce_cell_count "false"#@ set compile_new_optimization "false"#@#@#@ set ldd_return_val 0#@ if { [string compare $dc_shell_mode "default"] == 0 } {#@ set ldd_script ${synopsys_root}/auxx/syn/scripts/list_duplicate_designs.dcsh#@ alias list_duplicate_designs "include -quiet ldd_script; dc_shell_status = ldd_return_val "#@#@ }#@ if { [string compare $dc_shell_mode "tcl"] == 0 } {#@ set ldd_script ${synopsys_root}/auxx/syn/scripts/list_duplicate_designs.tcl#@ alias list_duplicate_designs "source $ldd_script; set dc_shell_status $ldd_return_val "#@ }#@#@#@ set compile_log_format " %elap_time %area %wns %tns %drc %endpoint";#@#@ set compile_top_all_paths "false"#@ alias compile_inplace_changed_list_file_name reoptimize_design_changed_list_file_name#@ ##@ # These variables affects compile, report_timing and report_constraints#@ # commands.#@ ##@ set enable_recovery_removal_arcs "false"#@ set timing_report_attributes {dont_touch dont_use map_only size_only ideal_net}#@#@ ##@ # Multibit Variable Group:#@ ##@ # These variables affect the multibit mapping functionality#@ ##@#@ set bus_multiple_separator_style ","#@#@ ##@ # Estimator Variable Group:#@ ##@ # These variables affect the designs created by the ESTIMATE command.#@ ##@ set estimate_resource_preference "fast"#@ alias est_resource_preference estimate_resource_preference#@ set lbo_lfo_enable_at_pin_count 3#@ set lbo_cells_in_regions "false"#@#@ # Synthetic Library Group:#@ ##@ # These variable affect synthetic library processing.#@ ##@ set cache_dir_chmod_octal "777"#@ set cache_file_chmod_octal "666"#@ set cache_read "~"#@ set cache_read_info "false"#@ set cache_write "~"#@ set cache_write_info "false"#@ set dw_prefer_mc_inside "false"#@ set mgi_scratch_directory "designware_generator"#@ set synlib_disable_limited_licenses "true"#@ set synlib_dont_get_license {}#@ set synlib_evaluation_mode "false"#@ set synlib_library_list {DW01 DW02 DW03 DW04 DW05 DW06 DW07 DW08}#@ set synlib_model_map_effort "medium"#@ set synlib_optimize_non_cache_elements "true"#@ set synlib_prefer_ultra_license "false"#@ set synlib_sequential_module "default"#@ set synlib_wait_for_design_license {}#@#@ ##@ # Insert_DFT Variable Group:#@ ##@ set test_default_client_order [list]#@ set test_point_keep_hierarchy "false"#@ set insert_dft_clean_up "true"#@ set insert_test_design_naming_style "%s_test_%d"#@ # /*insert_test_scan_chain_only_one_clock = "false"#@ # Replace by command line option (star 17215) -- Denis Martin 28-Jan-93*/#@ set test_clock_port_naming_style "test_c%s"#@ set test_scan_clock_a_port_naming_style "test_sca%s"#@ set test_scan_clock_b_port_naming_style "test_scb%s"#@ set test_scan_clock_port_naming_style "test_sc%s"#@ set test_scan_enable_inverted_port_naming_style "test_sei%s"#@ set test_scan_enable_port_naming_style "test_se%s"#@ set test_scan_in_port_naming_style "test_si%s%s"#@ set test_scan_out_port_naming_style "test_so%s%s"#@ set test_non_scan_clock_port_naming_style "test_nsc_%s"#@ set test_default_min_fault_coverage 95#@ set test_dedicated_subdesign_scan_outs "true"#@ set test_disable_find_best_scan_out "false"#@ set test_dont_fix_constraint_violations "false"#@ set test_isolate_hier_scan_out 0#@ set test_mode_port_naming_style "test_mode%s"#@ set test_mode_port_inverted_naming_style "test_mode_i%s"#@ set compile_dont_use_dedicated_scanout 1#@ set test_mux_constant_so "false"#@#@ ##@ # Analyze_Scan Variable Group:#@ ##@ # These variables affect the designs created by the PREVIEW_SCAN command.#@ ##@ set test_preview_scan_shows_cell_types "false"#@ set test_scan_link_so_lockup_key "l"#@ set test_scan_link_wire_key "w"#@ set test_scan_segment_key "s"#@ set test_scan_true_key "t"#@ set test_jump_over_bufs_invs "true"#@#@ ##@ # bsd Variable Group:#@#@ # These variables affect the report generated by the check_bsd command#@ # and the BSDLout generated by the write_bsdl command.#@ ##@ set test_user_test_data_register_naming_style "UTDR%d"#@#@ set test_user_defined_instruction_naming_style "USER%d"#@#@ set test_bsdl_default_suffix_name "bsdl"#@#@ set test_bsdl_max_line_length 80#@#@ set test_cc_ir_masked_bits 0#@#@ set test_cc_ir_value_of_masked_bits 0#@#@ set test_bsd_allow_tolerable_violations "false"#@ set test_bsd_optimize_control_cell "false"#@ set test_bsd_control_cell_drive_limit 0#@ set test_bsd_manufacturer_id 0#@ set test_bsd_part_number 0#@ set test_bsd_version_number 0#@#@#@ ##@ # TestManager Variable Group:#@ ##@ # These variables affect the TestManager methodology.#@ ##@ set multi_pass_test_generation "false"#@#@ ##@ # TestSim Variable Group:#@ ##@ # These variables affect the TestSim behavior.#@ ##@ # set testsim_print_stats_file "true"#@#@ # Test DRC Variable Group:#@ ##@ # These variables affect the check_test command.#@ ##@ set test_capture_clock_skew "small_skew"#@ set test_allow_clock_reconvergence "true"#@ set test_check_port_changes_in_capture "true"#@ set test_infer_slave_clock_pulse_after_capture "infer"#@#@ ##@ # Test Variable Group:#@ ##@ # These variables affect the rtldrc, check_test, write_test_protocol#@ # and write_test command.#@ ##@ set test_default_delay 5.0#@ set test_default_bidir_delay 55.0#@ set test_default_strobe 95.0#@ set test_default_strobe_width 0.0#@ set test_default_period 100.0#@ set test_default_scan_style "multiplexed_flip_flop"#@ set test_stil_netlist_format "db"#@ set test_stil_multiclock_capture_procedures "false"#@ set test_stil_max_line_length 72#@ set test_write_four_cycle_stil_protocol "false"#@ set test_protocol_add_cycle "true"#@ set test_rtldrc_latch_check_style "default"#@#@ ##@ # JTAG variable group (associated with the insert_jtag command):#@ ##@ # These variables are associated with JTAG synthesis.#@ ##@ set jtag_port_drive_limit 6#@ set jtag_manufacturer_id 0#@ set jtag_version_number 0#@ set jtag_part_number 65535#@ set jtag_test_data_in_port_naming_style "jtag_tdi%s"#@ set jtag_test_data_out_port_naming_style "jtag_tdo%s"#@ set jtag_test_mode_select_port_naming_style "jtag_tms%s"#@ set jtag_test_clock_port_naming_style "jtag_tck%s"#@ set jtag_test_reset_port_naming_style "jtag_trst%s"#@#@#@#@ ##@ # Create_Test_Patterns Variable Group:#@ ##@ # These variables affect the create_test_patterns command.#@ ##@ # From Peace on, the "atpg_test_asynchronous_pins" is obsolete#@ # set atpg_test_asynchronous_pins "true"#@#@ set atpg_bidirect_output_only "false"#@#@#@ ##@ # Write_Test Variable Group:#@ ##@ # These variables affect output of the WRITE_TEST command.#@ ##@ set write_test_input_dont_care_value "X"#@ set write_test_vector_file_naming_style "%s_%d.%s"#@ set write_test_scan_check_file_naming_style "%s_schk.%s"#@ set write_test_pattern_set_naming_style "TC_Syn_%d"#@ set write_test_max_cycles 0#@ set write_test_max_scan_patterns 0#@ # /*retain "tssi_ascii" (equivalent to "tds") for backward compatability */#@ set write_test_formats {synopsys tssi_ascii tds verilog vhdl wgl}#@ set write_test_include_scan_cell_info "true"#@ set write_test_round_timing_values "true"#@#@ ##@ # Schematic and EDIF and Hdl Variable Groups:#@ ##@ # These variables affect the schematics created by the#@ # create_schematic command, define the behavior of the#@ # DC system EDIF interface, and are for controlling hdl#@ # reading.#@ ##@ set bus_dimension_separator_style {][}#@ set bus_naming_style {%s[%d]}#@#@#@ ##@ # Schematic and EDIF Variable Groups:#@ ##@ # These variables affect the schematics created by the#@ # create_schematic command and define the behavior of#@ # the DC system EDIF interface.#@ ##@ set bus_range_separator_style ":"#@#@#@ ##@ # EDIF and Io Variable Groups:#@ ##@ # These variables define the behavior of the DC system EDIF interface and#@ # define the behavior of the DC system interfaces, i.e. LSI, Mentor, TDL, SGE,# etc.#@#@ set bus_inference_descending_sort "true"#@ set bus_inference_style ""#@ set write_name_nets_same_as_ports "false"#@ ##@ # Schematic Variable Group:#@ ##@ # These variables affect the schematics created by the#@ # create_schematic command.#@ ##@ set font_library "1_25.font"#@ set generic_symbol_library "generic.sdb"#@ set gen_max_ports_on_symbol_side 0#@ set duplicate_ports "false"#@ set sheet_sizes {A B C D E infinite mentor_maximum sge_maximum}#@ set single_group_per_sheet "false"#@ set use_port_name_for_oscs "true"#@ set gen_bussing_exact_implicit "false"#@ set gen_cell_pin_name_separator "/"#@ set gen_max_compound_name_length 256#@ set gen_show_created_symbols "false"#@ set gen_match_ripper_wire_widths "false"#@ set gen_show_created_busses "false"#@ set gen_dont_show_single_bit_busses "false"#@ set gen_single_osc_per_name "false"#@ set gen_create_netlist_busses "true"#@ # This setting will be overwritten to true below when using#@ # Design Vision or Psyn Gui#@ set sort_outputs "false"#@ if { ( [string compare $synopsys_program_name "design_vision"] == 0 ) ||#@ ( [string compare $synopsys_program_name "psyn_gui"] == 0 ) } {#@ set dv_enable_conservative_invalidate "true"#@ }#@ set gen_open_name_prefix "Open"#@ set gen_open_name_postfix ""#@ set default_schematic_options "-size infinite"#@ # This setting makes gen use the old way to annotate schematics for#@ # everything except sheets, which is fast enough.#@ ##@ set annotation_control 64#@#@ ##@ # Plot Variable Group:#@ ##@ # These variables define the operating system and plotter#@ # interface to the Design Compiler. These should be set at#@ # installation time, if needed, and then changed only if you#@ # start using a new type of plotter.#@ ##@ # These four variables must be changed if you use a larger or#@ # smaller plotter or printer:#@ ##@ # plotter_maxx, plotter_maxy, plotter_minx, plotter_miny#@ ##@ # See the group of site-specific variables at the top of this#@ # file to set the name of your printer or plotter.#@ ##@ ##@#@ set plot_orientation "best_fit"#@ set plotter_maxx 584#@ set plotter_maxy 764#@ set plotter_minx 28#@ set plotter_miny 28#@ set plot_scale_factor 100#@ set plot_box "false"#@#@#@ ##@ # Io Variable Group:#@ ##@ # These variables define the behavior of the DC system#@ # interfaces, i.e. LSI, Mentor, TDL, SGE, etc.#@ ##@ set db2sge_output_directory ""#@ set db2sge_scale "2"#@ set db2sge_overwrite "true"#@ set db2sge_display_symbol_names "false"#@#@#@ set db2sge_display_pin_names "false"#@ set db2sge_display_instance_names "false"#@ set db2sge_use_bustaps "false"#@ set db2sge_use_compound_names "true"#@ set db2sge_bit_type "std_logic"#@ set db2sge_bit_vector_type "std_logic_vector"#@ set db2sge_one_name "'1'"#@ set db2sge_zero_name "'0'"#@ set db2sge_unknown_name "'X'"#@ set db2sge_target_xp "false"#@ set db2sge_tcf_package_file "synopsys_tcf.vhd"#@ set db2sge_use_lib_section ""#@ set db2sge_script ""#@ set db2sge_command ""#@ set equationout_and_sign "*"#@ set equationout_or_sign "+"#@ set equationout_postfix_negation "true"#@ set lsiin_net_name_prefix "NET_"#@ set lsiout_inverter_cell ""#@ set lsiout_upcase "true"#@ set mentor_bidirect_value "INOUT"#@ set mentor_do_path ""#@ set mentor_input_output_property_name "PINTYPE"#@ set mentor_input_value "IN"#@ set mentor_logic_one_value "1SF"#@ set mentor_logic_zero_one_property_name "INIT"#@ set mentor_logic_zero_value "0SF"#@ set mentor_output_value "OUT"#@ set mentor_primitive_property_name "PRIMITIVE"#@ set mentor_primitive_property_value "MODULE"#@ set mentor_reference_property_name "COMP"#@ set mentor_search_path ""#@ set mentor_write_symbols "true"#@ set pla_read_create_flip_flop "false"#@ set tdlout_upcase "true"#@ set xnfout_constraints_per_endpoint "50"#@ set xnfout_default_time_constraints true#@ set xnfout_clock_attribute_style "CLK_ONLY"#@ set xnfout_library_version ""#@ set xnfin_family "4000"#@ set xnfin_ignore_pins "GTS GSR GR"#@ set xnfin_dff_reset_pin_name "RD"#@ set xnfin_dff_set_pin_name "SD"#@ set xnfin_dff_clock_enable_pin_name "CE"#@ set xnfin_dff_data_pin_name "D"#@ set xnfin_dff_clock_pin_name "C"#@ set xnfin_dff_q_pin_name "Q"#@#@#@ ##@ # EDIF Variable Group:#@ ##@ # These variables define the behavior of the DC system#@ # EDIF interface.#@ ##@ set bus_extraction_style {%s[%d:%d]}#@ set edifin_autoconnect_offpageconnectors "false"#@ set edifin_autoconnect_ports "false"#@ set edifin_dc_script_flag ""#@ set edifin_delete_empty_cells "true"#@ set edifin_delete_ripper_cells "true"#@ set edifin_ground_net_name ""#@ set edifin_ground_net_property_name ""#@ set edifin_ground_net_property_value ""#@ set edifin_ground_port_name ""#@ set edifin_instance_property_name ""#@ set edifin_portinstance_disabled_property_name ""#@ set edifin_portinstance_disabled_property_value ""#@ set edifin_portinstance_property_name ""#@ set edifin_power_net_name ""#@ set edifin_power_net_property_name ""#@ set edifin_power_net_property_value ""#@ set edifin_power_port_name ""#@ set edifin_use_identifier_in_rename "false"#@ set edifin_view_identifier_property_name ""#@ set edifin_lib_logic_1_symbol ""#@ set edifin_lib_logic_0_symbol ""#@ set edifin_lib_in_port_symbol ""#@ set edifin_lib_out_port_symbol ""#@ set edifin_lib_inout_port_symbol ""#@ set edifin_lib_in_osc_symbol ""#@ set edifin_lib_out_osc_symbol ""#@ set edifin_lib_inout_osc_symbol ""#@ set edifin_lib_mentor_netcon_symbol ""#@ set edifin_lib_ripper_bits_property ""#@ set edifin_lib_ripper_bus_end ""#@ set edifin_lib_ripper_cell_name ""#@ set edifin_lib_ripper_view_name ""#@ set edifin_lib_route_grid 1024#@ set edifin_lib_templates {}#@ set edifout_dc_script_flag ""#@ set edifout_design_name "Synopsys_edif"#@ set edifout_designs_library_name "DESIGNS"#@ set edifout_display_instance_names "false"#@ set edifout_display_net_names "false"#@ set edifout_external "true"#@ set edifout_external_graphic_view_name "Graphic_representation"#@ set edifout_external_netlist_view_name "Netlist_representation"#@ set edifout_external_schematic_view_name "Schematic_representation"#@ set edifout_ground_name "logic_0"#@ set edifout_ground_net_name ""#@ set edifout_ground_net_property_name ""#@ set edifout_ground_net_property_value ""#@ set edifout_ground_pin_name "logic_0_pin"#@ set edifout_ground_port_name "GND"#@ set edifout_instance_property_name ""#@ set edifout_instantiate_ports "false"#@ set edifout_library_graphic_view_name "Graphic_representation"#@ set edifout_library_netlist_view_name "Netlist_representation"#@ set edifout_library_schematic_view_name "Schematic_representation"#@ set edifout_merge_libraries "false"#@ set edifout_multidimension_arrays "false"#@ set edifout_name_oscs_different_from_ports "false"#@ set edifout_name_rippers_same_as_wires "false"#@ set edifout_netlist_only "false"#@ set edifout_no_array "false"#@ set edifout_numerical_array_members "false"#@ set edifout_pin_direction_in_value ""#@ set edifout_pin_direction_inout_value ""#@ set edifout_pin_direction_out_value ""#@ set edifout_pin_direction_property_name ""#@ set edifout_pin_name_property_name ""#@ set edifout_portinstance_disabled_property_name ""#@ set edifout_portinstance_disabled_property_value ""#@ set edifout_portinstance_property_name ""#@ set edifout_power_and_ground_representation "cell"#@ set edifout_power_name "logic_1"#@ set edifout_power_net_name ""#@ set edifout_power_net_property_name ""#@ set edifout_power_net_property_value ""#@ set edifout_power_pin_name "logic_1_pin"#@ set edifout_power_port_name "VDD"#@ set edifout_skip_port_implementations "false"#@ set edifout_target_system ""#@ set edifout_top_level_symbol "true"#@ set edifout_translate_origin ""#@ set edifout_unused_property_value ""#@ set edifout_write_attributes "false"#@ set edifout_write_constraints "false"#@ set edifout_write_properties_list {}#@ set read_name_mapping_nowarn_libraries {}#@ set write_name_mapping_nowarn_libraries {}#@#@ ##@ # Hdl and Vhdlio Variable Groups:#@ ##@ # These variables are for controlling hdl reading, writing,#@ # and optimizing.#@ ##@ set hdlin_enable_presto "TRUE"#@ set hdlin_enable_rtldrc_info "false"#@ set hdlin_enable_vpp "false"#@ set hdlin_escape_special_names "FALSE"#@ set hdlin_allow_mixed_blocking_and_nonblocking "TRUE"#@ set hdlin_auto_full_case "TRUE"#@ set hdlin_auto_parallel_case_early "TRUE"#@ set hdlin_black_box_pin_hdlc_style "TRUE"#@ set hdlin_branch_optimization "TRUE"#@ set hdlin_build_selectop_for_var_index "FALSE"#@ set hdlin_ff_always_async_set_reset "TRUE"#@ set hdlin_ff_always_sync_set_reset "FALSE"#@ set hdlin_generate_naming_style "%s_%d"#@ set hdlin_generate_separator_style "_"#@ set hdlin_group_selectors "TRUE"#@ set hdlin_hide_resource_line_numbers "FALSE"#@ set hdlin_infer_block_local_latches "TRUE"#@ set hdlin_infer_comparators "TRUE"#@ set hdlin_infer_decoders "FALSE"#@ set hdlin_infer_enumerated_types "FALSE"#@ set hdlin_infer_function_local_latches "FALSE"#@ set hdlin_infer_multibit "default_none"#@ set hdlin_infer_mux "default"#@ set hdlin_keep_feedback "FALSE"#@ set hdlin_keep_inv_feedback "TRUE"#@ set hdlin_latch_always_async_set_reset "FALSE"#@ set hdlin_link_design "FALSE"#@ set hdlin_loop_invariant_code_motion "TRUE"#@ set hdlin_map_to_entity "TRUE"#@ set hdlin_map_to_module "TRUE"#@ set hdlin_map_to_operator "TRUE"#@ set hdlin_merge_nested_conditional_statements "false"#@ set hdlin_module_arch_name_splitting "FALSE"#@ set hdlin_mux_oversize_ratio 100#@ set hdlin_mux_size_limit 32#@ set hdlin_mux_size_min 2#@ set hdlin_netlist_transform "TRUE"#@ set hdlin_no_adder_feedthroughs "TRUE"#@ set hdlin_no_sequential_mapping "FALSE"#@ set hdlin_one_hot_one_cold_on "TRUE"#@ set hdlin_optimize_array_references "TRUE"#@ set hdlin_optimize_case_default "TRUE"#@ set hdlin_optimize_enum_types "FALSE"#@ set hdlin_optimize_shift_expressions "TRUE"#@ set hdlin_optimize_slice_op "TRUE"#@ set hdlin_preserve_vpp_files "false"#@ set hdlin_print_modfiles "FALSE"#@ set hdlin_redundancy_elimination "TRUE"#@ set hdlin_reg_report_length 60#@ set hdlin_register_report_depth 3#@ set hdlin_replace_synthetic "FALSE"#@ set hdlin_report_enumerated_types "TRUE"#@ set hdlin_report_inferred_modules "true"#@ set hdlin_report_mux_op "TRUE"#@ set hdlin_report_syn_cell "FALSE"#@ set hdlin_report_tri_state "TRUE"#@ set hdlin_selector_simplify_effort 1#@ set hdlin_seqmap_search_depth 3#@ set hdlin_call_stack_depth 1000#@ set hdlin_check_user_full_case "TRUE"#@ set hdlin_check_user_parallel_case "TRUE"#@ set hdlin_compare_const_with_gates "TRUE"#@ set hdlin_compare_eq_with_gates "TRUE"#@ set hdlin_prohibit_nontri_multiple_drivers "TRUE"#@ set hdlin_decoder_max_input_width 31#@ set hdlin_decoder_min_input_width 5#@ set hdlin_decoder_min_use_percentage 90#@ set hdlin_mux_size_min 2#@ set hdlin_dyn_array_bnd_check "FALSE"#@ set hdlin_share_all_operators "FALSE"#@ set hdlin_subprogram_default_values "FALSE"#@ set hdlin_template_naming_style_variable "%s_%p"#@ set hdlin_template_parameter_style_variable "%s%d"#@ set hdlin_template_separator_style_variable "_"#@ set hdlin_array_instance_naming_style {%s[%d]}#@ set hdlin_translate_off_on "TRUE"#@ set hdlin_translate_off_skip_text "false"#@ set hdlin_unsigned_rem "TRUE"#@ set hdlin_upcase_names "FALSE"#@ set hdlin_use_carry_in "FALSE"#@ set hdlin_use_syn_shifter "FALSE"#@ set hdlin_verbose_cell_naming "FALSE"#@ set hdlin_vhdl93_concat "true"#@ set hdlin_vhdl_93 "TRUE"#@ set hdlin_vpp_temporary_directory ""#@ set hdlin_vrlg_std 2000#@ set hdlin_warn_array_bound "TRUE"#@ set hdlin_warn_implicit_wires "TRUE"#@ set hdlin_warn_mixed_blocking_and_nonblocking "TRUE"#@ set hdlin_warn_sens_list "TRUE"#@ set hdlin_while_loop_iterations 1000#@ set hdlin_work_directory ""#@#@ set hdlin_advisor_directory "."#@ set bus_minus_style "-%d"#@ set hdlin_write_gtech_design_directory "."#@ set hdlin_enable_analysis_info "false"#@ set hdlin_hide_resource_line_numbers FALSE#@ set hdlin_reg_report_length 60#@ set hdlin_auto_save_templates FALSE#@ set hdlin_replace_synthetic FALSE#@ set hdlin_dont_check_param_width FALSE#@ set hdlin_latch_always_async_set_reset FALSE#@ set hdlin_ff_always_sync_set_reset FALSE#@ set hdlin_ff_always_async_set_reset TRUE#@ set hdlin_check_no_latch FALSE#@ set hdlin_report_inferred_modules "true"#@ set hdlin_reg_report_length 60#@ set hdlin_translate_off_skip_text false#@ set hdlin_keep_feedback FALSE#@ set hdlin_keep_inv_feedback TRUE#@ set hdlin_infer_mux "default"#@ set hdlin_merge_nested_conditional_statements false#@ set hdlin_dont_infer_mux_for_resource_sharing "true"#@ set hdlin_mux_oversize_ratio 100#@ set hdlin_mux_size_limit 32#@ set hdlin_infer_multibit "default_none"#@ set hdlin_enable_vpp false#@ set hdlin_preserve_vpp_files false#@ set hdlin_vpp_temporary_directory ""#@ set hdlin_vhdl93_concat "true"#@ set hdlin_enable_rtldrc_info "false"#@ set hdl_preferred_license ""#@ set hdl_keep_licenses "true"#@ set hlo_resource_allocation "constraint_driven"#@ set hlo_transform_constant_multiplication "false"#@ set hlo_minimize_tree_delay true#@ set hlo_resource_implementation "use_fastest"#@ set hlo_share_common_subexpressions true#@ set hlo_share_effort low#@ set hlo_ignore_priorities false#@ set sdfout_top_instance_name ""#@ set sdfout_time_scale 1.0#@ set sdfout_min_rise_net_delay 0.#@ set sdfout_min_fall_net_delay 0.#@ set sdfout_min_rise_cell_delay 0.#@ set sdfout_min_fall_cell_delay 0.#@ set sdfout_write_to_output "false"#@ set sdfout_allow_non_positive_constraints "false"#@ set sdfin_top_instance_name ""#@ set sdfin_min_rise_net_delay 0.#@ set sdfin_min_fall_net_delay 0.#@ set sdfin_min_rise_cell_delay 0.#@ set sdfin_min_fall_cell_delay 0.#@ set sdfin_rise_net_delay_type "maximum"#@ set sdfin_fall_net_delay_type "maximum"#@ set sdfin_rise_cell_delay_type "maximum"#@ set sdfin_fall_cell_delay_type "maximum"#@ set site_info_file ${synopsys_root}/admin/license/site_info#@ if { [string compare $dc_shell_mode "tcl"] == 0 } {#@ alias site_info sh cat $site_info_file#@ } else {#@ alias site_info "sh cat site_info_file"#@ }#@ set hdl_naming_threshold 20#@ set template_naming_style "%s_%p"#@ set template_parameter_style "%s%d"#@ set template_separator_style "_"#@ set design_library_file ".synopsys_vss.setup"#@ set verilogout_equation "false"#@ set verilogout_ignore_case "false"#@ set verilogout_no_tri "false"#@ set verilogout_single_bit "false"#@ set verilogout_higher_designs_first "FALSE"#@ set verilogout_levelize "FALSE"#@ set verilogout_include_files {}#@ set verilogout_unconnected_prefix "SYNOPSYS_UNCONNECTED_"#@ set verilogout_show_unconnected_pins "FALSE"#@ set verilogout_no_negative_index "FALSE"#@ set vhdlout_architecture_name "SYN_%a_%u"#@ set vhdlout_bit_type "std_logic"#@ set vhdlout_bit_type_resolved "TRUE"#@ set vhdlout_bit_vector_type "std_logic_vector"#@ set vhdlout_conversion_functions {}#@ set vhdlout_dont_write_types "FALSE"#@ set vhdlout_equations "FALSE"#@ set vhdlout_one_name "'1'"#@ set vhdlout_package_naming_style "CONV_PACK_%d"#@ set vhdlout_preserve_hierarchical_types "VECTOR"#@ set vhdlout_separate_scan_in "FALSE"#@ set vhdlout_single_bit "USER"#@ set vhdlout_target_simulator ""#@ set vhdlout_three_state_name "'Z'"#@ set vhdlout_three_state_res_func ""#@ set vhdlout_time_scale 1.0#@ set vhdlout_top_configuration_arch_name "A"#@ set vhdlout_top_configuration_entity_name "E"#@ set vhdlout_top_configuration_name "CFG_TB_E"#@ set vhdlout_unknown_name "'X'"#@ set vhdlout_upcase "FALSE"#@ set vhdlout_use_packages {IEEE.std_logic_1164}#@ set vhdlout_wired_and_res_func ""#@ set vhdlout_wired_or_res_func ""#@ set vhdlout_write_architecture "TRUE"#@ set vhdlout_write_components "TRUE"#@ set vhdlout_write_entity "TRUE"#@ set vhdlout_write_top_configuration "FALSE"#@ set vhdlout_synthesis_off "TRUE"#@ set vhdlout_zero_name "'0'"#@ set vhdlout_levelize "FALSE"#@ set vhdlout_dont_create_dummy_nets "FALSE"#@ set vhdlout_follow_vector_direction "FALSE"#@#@#@ # vhdl netlist reader variables#@ set enable_vhdl_netlist_reader "FALSE"#@#@ # variables pertaining to VHDL library generation#@ set vhdllib_timing_mesg "true"#@ set vhdllib_timing_xgen "false"#@ set vhdllib_timing_checks "true"#@ set vhdllib_negative_constraint "false"#@ set vhdllib_glitch_handle "true"#@ set vhdllib_pulse_handle "use_vhdllib_glitch_handle"#@ # /*vhdllib_architecture = {FTBM, UDSM, FTSM, FTGS, VITAL}; */#@ set vhdllib_architecture {UDSM, FTSM, FTGS, VITAL}#@ set vhdllib_tb_compare 0#@ set vhdllib_tb_x_eq_dontcare FALSE#@ set vhdllib_logic_system "ieee-1164"#@ set vhdllib_logical_name ""#@#@ # variables pertaining to technology library processing#@ set read_db_lib_warnings FALSE#@ set read_translate_msff TRUE#@ set libgen_max_differences -1#@#@ ##@ # View Variable Group:#@ ##@ # These variables define the behavior of the Design_Analyzer.#@ # Each user may wish to customize the cursor color, or , , etc. of the#@ # viewer in his/her own .synopsys file.#@ ##@ ##@ set view_maximum_route_grids 0#@ set view_dialogs_modal "true"#@ set view_disable_error_windows "false"#@ set view_error_window_count 6#@ set view_log_file ""#@ set view_busy_during_selection "true"#@ set view_set_cursor_area 5#@ set view_cache_images "true"#@ set view_draw_text_breakpoint 0.01#@ set view_use_integer_scaling "false"#@ set view_use_x_routines "true"#@ set view_disable_output "false"#@ #set view_arch_types {sparcOS5, hpux10, apollo, decmips, hp700, mips, necmips, rs6000, sgimips, sonymips, sun3, sparc}#@ set view_icon_path ${init_path}/icons#@ set view_background "black"#@ set view_disable_cursor_warping "true"#@ set view_watcher ${bin_path}/da_watcher_exec#@ set da_ref_manual "synth/daptr/toc.pdf"#@ set view_command_win_max_lines 1000#@ set view_select_separator " - "#@ set view_select_default_message "Left Button: Select - Middle Button: Add/Modify Select - Right Button: Menu"#@ set view_on_line_doc_cmd ${synopsys_root}/sold#@ set view_info_search_cmd ${synopsys_root}/infosearch/scripts/InfoSearch#@ set view_script_submenu_items {}#@ set x11_set_cursor_number -1#@ set x11_set_cursor_foreground ""#@ set x11_set_cursor_background ""#@ set view_set_selecting_color ""#@ set view_use_small_cursor ""#@ # added for star 12763#@ set view_tools_menu_items {}#@ # affect the HDL Text Viewer#@ set text_unselect_on_button_press "true"#@ set text_editor_command "xterm -fn 8x13 -e vi %s &"#@ set test_design_analyzer_uses_insert_scan "true"#@#@ ##@ # If you like emacs, uncomment the next line#@ # set text_editor_command "emacs -fn 8x13 %s &" ;#@#@ # You can delete pairs from this list, but you can't add new ones#@ # unless you also update the UIL files. So, customers can not add#@ # dialogs to this list, only Synopsys can do that.#@ ##@ set view_independent_dialogs { "test_report", " Test Reports ", "report_print", " Report ", "report_options", " Report Options ", "report_win", " Report Output ", "manual_page", " Manual Page " }#@#@ # if color Silicon Graphics workstation#@ if { [info exists x11_vendor_string] && [info exists x11_is_color]} {#@ if { $x11_vendor_string == "Silicon" && $x11_is_color == "true" } {#@ set x11_set_cursor_foreground "magenta"#@ set view_use_small_cursor "true"#@ set view_set_selecting_color "white"#@ }#@ }#@#@ # if running on an Apollo machine#@ set found_x11_vendor_string_apollo 0#@ set found_arch_apollo 0#@ if { [info exists x11_vendor_string]} {#@ if { $x11_vendor_string == "Apollo "} {#@ set found_x11_vendor_string_apollo 1#@ }#@ }#@ if { [info exists arch]} {#@ if { $arch == "apollo"} {#@ set found_arch_apollo 1#@ }#@ }#@ if { $found_x11_vendor_string_apollo == 1 || $found_arch_apollo == 1} {#@ set enable_page_mode "false"#@ } else {#@ set enable_page_mode "true"#@ }#@#@ # don't work around this bug on the Apollo#@ if { $found_x11_vendor_string_apollo == 1} {#@ set view_extend_thick_lines "false"#@ } else {#@ set view_extend_thick_lines "true"#@ }#@#@ ##@ # Suffix Variable Group:#@ ##@ # Suffixes recognized by the Design Analyzer menu in file choices#@ ##@ if { $synopsys_program_name == "design_vision" || $synopsys_program_name == "psyn_gui" } {#@ # For star 93040 do NOT include NET in list, 108991 : pdb suffix added#@ set view_read_file_suffix {db gdb sdb pdb edif eqn fnc lsi mif pla st tdl v vhd vhdl xnf}#@ } else {#@ set view_read_file_suffix {db gdb sdb edif eqn fnc lsi mif NET pla st tdl v vhd vhdl xnf}#@ }#@#@ set view_analyze_file_suffix {v vhd vhdl}#@ set view_write_file_suffix {gdb db sdb do edif eqn fnc lsi NET neted pla st tdl v vhd vhdl xnf}#@ set view_execute_script_suffix {.script .scr .dcs .dcv .dc .con}#@ set view_arch_types {sparcOS5 hpux10 rs6000 sgimips}#@#@ ##@ # links_to_layout Variable Group:#@ ##@ # These variables affect the read_timing, write_timing#@ # set_annotated_delay, compile, create_wire_load and reoptimize_design#@ # commands.#@ ##@ set rtl_load_resistance_factor 0.0#@ set auto_wire_load_selection "true"#@ set compile_create_wire_load_table "false"#@#@ # power Variable Group:#@ ##@ # These variables affect the behavior of power analysis.#@ ##@ ##@#@ set power_keep_license_after_power_commands "false"#@ set power_rtl_saif_file "power_rtl.saif"#@ set power_sdpd_saif_file "power_sdpd.saif"#@ set power_preserve_rtl_hier_names "false"#@ set power_do_not_size_icg_cells "false"#@ set power_hdlc_do_not_split_cg_cells "false"#@#@ # BC Variable Group:#@ ##@ # These variables affect the BC behavior#@ ##@ ##@#@ ##@ # BCView#@ ##@ set bc_enable_analysis_info "false"#@#@ ##@ # Scheduling#@ ##@ set bc_enable_chaining "true"#@ set bc_enable_multi_cycle "true"#@ set bc_enable_speculative_execution "false"#@#@#@ ##@ # Control Generation#@ ##@ set bc_fsm_coding_style "one_hot"#@#@ ##@ # Netlisting#@ ##@ #Ki-Seok: removed the following 3 variables: Jan. 1999#@ #/*#@ #set bc_no_reset_on_datapath "true"#@ #set bc_clears_all_registers "false"#@ #set bc_connect_reset "true"#@ #*/#@#@ #/*#@ # * Timing (bc_time_design and timing estimates during scheduling)#@ # */#@ #/* Removed by Suhrid A. Wadekar Feb. 11, 1999.#@ # * bc_preserved_functions_map_effort is no longer supported#@ # */#@ #/*#@ #set bc_preserved_functions_map_effort "medium"#@ #*/#@ set bc_time_all_sequential_op_bindings "false"#@ set bc_estimate_mux_input 4#@ set bc_estimate_timing_effort "high"#@#@ #/*#@ # * Memories#@ # */#@ set bc_allow_shared_memories "false"#@ set bc_constrain_signal_memories "false"#@ set bc_detect_memory_accesses "true"#@ set bc_detect_array_accesses "true"#@ set bc_chain_read_into_mem "true"#@ set bc_chain_read_into_oper "true"#@#@ #/*#@ # * Logic grouping#@ # */#@ set bc_group_eql_logic "true"#@ set bc_group_index_logic "true"#@ set bc_use_registerfiles "false"#@#@ ##@ # Reporting#@ ##@ set bc_report_filter ""#@#@ ##@ # RTLout debug mode#@ ##@ set vhdlout_debug_mode "false"#@ set verilogout_debug_mode "false"#@#@ ##@ # RTLout i/o trace#@ ##@ set bc_add_io_trace "false"#@#@ # Synthesizable RTLOUT variables#@ set bc_synrtl_map_to_gtech "true"#@ set bc_synrtl_write_precompiled_designware "true"#@ set bc_synrtl_write_preserved_functions "true"#@ set bc_synrtl_write_dcsh_and_dctcl "false"#@#@ # SystemC related variables#@ set systemcout_levelize "true"#@ set systemcout_debug_mode "false"#@#@ # ACS Variables#@ if { [info exists acs_work_dir] } {#@ set acs_work_dir [pwd]#@ set acs_hdl_source {}#@ set acs_verilog_extensions {.v}#@ set acs_vhdl_extensions {.vhd}#@ set acs_exclude_extensions {}#@ set acs_exclude_list {}#@ set acs_area_report_suffix "area"#@ set acs_budgeted_cstr_suffix "con"#@ set acs_compile_script_suffix "autoscr"#@ set acs_constraint_file_suffix "con"#@ set acs_cstr_report_suffix "cstr"#@ set acs_db_suffix "db"#@ set acs_log_file_suffix "log"#@ set acs_makefile_name "Makefile"#@ set acs_override_script_suffix "scr"#@ set acs_override_report_suffix "report"#@ set acs_qor_report_suffix "qor"#@ set acs_timing_report_suffix "tim"#@ set acs_user_compile_strategy_script_suffix "compile"#@ set acs_global_user_compile_strategy_script "default"#@ set acs_budget_script_file_suffix "btcl"#@ set acs_budget_output_file_suffix "btcl.out"#@ set acs_use_lsf "false"#@ set acs_script_mode "dctcl"#@ set acs_default_pass_name "pass"#@ set acs_lic_wait 0#@ set acs_num_parallel_jobs 1#@ set acs_make_exec "gmake"#@ set acs_make_args "set acs_make_args"#@ set acs_bsub_exec "bsub"#@ set acs_bsub_args "set acs_bsub_args"#@ set acs_user_budgeting_script "budget.scr"#@ set acs_bs_exec ""#@ set acs_tr_exec ""#@ set acs_dc_exec ""#@ set acs_use_default_delays "false"#@ set acs_use_dc_gate_level_budgeting "false"#@ set acs_use_autopartition "false"#@ set acs_autopart_max_percent "0.0"#@ set acs_autopart_max_area "0.0"#@ set arest_pincount_method "allcell"#@ set check_error_list [list CMD-004 CMD-006 CMD-007 CMD-008 CMD-009 CMD-010 CMD-011 CMD-012 CMD-014 CMD-015 CMD-016 CMD-019 CMD-026 CMD-031 CMD-037 DB-1 DCSH-11 DES-001 FILE-1 FILE-2 FILE-3 FILE-4 LINK-5 LINK-7 LINT-7 LINT-20 LNK-023 OPT-100 OPT-101 OPT-102 OPT-114 OPT-124 OPT-127 OPT-128 OPT-155 OPT-157 OPT-181 OPT-462 UI-11 UI-14 UI-15 UI-16 UI-17 UI-19 UI-20 UI-21 UI-22 UI-23 UI-40 UI-41 UID-4 UID-6 UID-7 UID-8 UID-9 UID-13 UID-14 UID-15 UID-19 UID-20 UID-25 UID-27 UID-28 UID-29 UID-30 UID-32 UID-58 UID-87 UID-103 UID-109 UID-270 UID-272 UID-403 UID-440 UID-444 UIO-2 UIO-3 UIO-4 UIO-25 UIO-65 UIO-66 UIO-75 UIO-94 UIO-95 EQN-6 EQN-11 EQN-15 EQN-16 EQN-18 EQN-20 ]#@ }#@#@ ##@ # eco variable group#@ ##@ # These variables affect ECO Compiler functionality#@ ##@ ##@ set eco_align_design_verbose "false"#@ set eco_allow_register_type_difference "false"#@ set eco_connect_resource_cell_inputs "true"#@ set eco_correspondence_analysis_verbose "false"#@ set eco_directives_verbose "false"#@ set eco_implement_effort_level "low"#@ set eco_instance_name_prefix "eco_"#@ set eco_recycle_verbose "true"#@ set eco_remap_register_verbose "false"#@ set eco_reuse_verbose "false"#@#@#@ ##@ # Variable Group Definitions:#@ ##@ # The group_variable() command groups variables for display#@ # in the "File/Defaults" dialog and defines groups of variables#@ # for the list() command.#@ ##@#@ set enable_instances_in_report_net "false"#@ # Set report options env variables#@ set view_report_interactive "true"#@ set view_report_output2file "false"#@ set view_report_append "true"#@#@ group_variable report_variables "enable_instances_in_report_net"#@ group_variable report_variables "view_report_interactive"#@ group_variable report_variables "view_report_output2file"#@ group_variable report_variables "view_report_append"#@#@ # "links_to_layout" variables are used by multiple commands#@ # auto_wire_load_selection is also in the "compile" variable group.#@ group_variable links_to_layout "auto_wire_load_selection"#@#@ # variables starting with "compile" are also in the compile variable group#@ group_variable links_to_layout "compile_dont_touch_annotated_cell_during_inplace_opt"#@#@ group_variable links_to_layout "compile_update_annotated_delays_during_inplace_opt"#@ group_variable links_to_layout "compile_create_wire_load_table"#@#@ group_variable links_to_layout "reoptimize_design_changed_list_file_name"#@ group_variable links_to_layout "sdfout_allow_non_positive_constraints"#@#@ ##@ # to find the XErrorDB and XKeySymDB for X11 file#@ set motif_files ${synopsys_root}/admin/setup#@ # set filename for logging input file#@ set filename_log_file "filenames.log"#@ # whether to delete the filename log after the normal exits#@ set exit_delete_filename_log_file "true"#@#@ # executable to fire off RTLA/BCV#@ set xterm_executable "xterm"#@#@ # "system" variables are used by multiple commands#@ group_variable system auto_link_disable#@ group_variable system auto_link_options#@ group_variable system command_log_file#@ group_variable system company#@ group_variable system compatibility_version#@#@ if { [string compare $dc_shell_mode "default"] == 0 } {#@ group_variable system "current_design"#@ group_variable system "current_instance"#@ group_variable system "dc_shell_status"#@ } else {#@ set current_design ""#@ set current_instance ""#@ group_variable system "current_design"#@ group_variable system "current_instance"#@ }#@#@ group_variable system "designer"#@ group_variable system "echo_include_commands"#@ group_variable system "enable_page_mode"#@ group_variable system "change_names_update_inst_tree"#@ group_variable system "change_names_dont_change_bus_members"#@ group_variable system "default_name_rules"#@ group_variable system "verbose_messages"#@ group_variable system "link_library"#@ group_variable system "physical_library"#@ group_variable system "link_force_case"#@ group_variable system "search_path"#@ group_variable system "synthetic_library"#@ group_variable system "target_library"#@ group_variable system "uniquify_naming_style"#@ group_variable system "suppress_errors"#@ group_variable system "find_converts_name_lists"#@ group_variable system "filename_log_file"#@ group_variable system "exit_delete_filename_log_file"#@ group_variable system "syntax_check_status"#@ group_variable system "context_check_status"#@#@ #/* "compile" variables are used by the compile command */#@ group_variable compile "compile_assume_fully_decoded_three_state_busses"#@ group_variable compile "compile_automatic_clock_phase_inference"#@ group_variable compile "compile_no_new_cells_at_top_level"#@ group_variable compile "compile_dont_touch_annotated_cell_during_inplace_opt"#@ group_variable compile "reoptimize_design_changed_list_file_name"#@ group_variable compile "compile_create_wire_load_table"#@ group_variable compile "compile_update_annotated_delays_during_inplace_opt"#@ group_variable compile "compile_instance_name_prefix"#@ group_variable compile "compile_instance_name_suffix"#@ group_variable compile "compile_negative_logic_methodology"#@ group_variable compile "compile_disable_hierarchical_inverter_opt"#@#@ group_variable compile "port_complement_naming_style"#@ group_variable compile "auto_wire_load_selection"#@ group_variable compile "rtl_load_resistance_factor"#@ group_variable compile "compile_implementation_selection"#@ group_variable compile "compile_use_fast_delay_mode"#@ group_variable compile "compile_use_low_timing_effort"#@ group_variable compile "compile_new_boolean_structure"#@ group_variable compile "compile_fix_cell_degradation"#@ group_variable compile "compile_mux_no_boundary_optimization"#@ group_variable compile "compile_create_mux_op_hierarchy"#@ group_variable compile "compile_preserve_subdesign_interfaces"#@ group_variable compile "compile_sequential_area_recovery"#@ group_variable compile "compile_delete_unloaded_sequential_cells"#@ group_variable compile "enable_recovery_removal_arcs"#@ group_variable compile "compile_checkpoint_filename"#@ group_variable compile "compile_checkpoint_cpu_interval"#@ group_variable compile "compile_checkpoint_phases"#@ group_variable compile "compile_checkpoint_pre_delay_filename"#@ group_variable compile "compile_checkpoint_pre_drc1_filename"#@ group_variable compile "compile_checkpoint_pre_drc2_filename"#@ group_variable compile "compile_checkpoint_pre_area_filename"#@ group_variable compile "compile_cpu_limit"#@ group_variable compile "compile_top_all_paths"#@ group_variable compile "compile_top_all_paths"#@ group_variable compile "default_port_connection_class"#@ group_variable compile "compile_dw_simple_mode"#@ group_variable compile "compile_simple_mode_block_effort"#@ group_variable compile "compile_new_optimization"#@#@#@ # "multibit" variables are used by the the multibit mapping functionality#@#@ group_variable multibit "bus_multiple_separator_style"#@#@ # "estimate" variables are used by the estimate command#@ # The estimate command also recognizes the "compile" variables.#@ group_variable estimate "estimate_resource_preference"#@#@ # "synthetic_library" variables#@ group_variable synlib "cache_dir_chmod_octal"#@ group_variable synlib "cache_file_chmod_octal"#@ group_variable synlib "cache_read"#@ group_variable synlib "cache_read_info"#@ group_variable synlib "cache_write"#@ group_variable synlib "cache_write_info"#@ group_variable synlib "dw_prefer_mc_inside"#@ group_variable synlib "hdlin_replace_synthetic"#@ group_variable synlib "mgi_scratch_directory"#@ group_variable synlib "synlib_disable_limited_licenses"#@ group_variable synlib "synlib_dont_get_license"#@ group_variable synlib "synlib_evaluation_mode"#@ group_variable synlib "synlib_model_map_effort"#@ group_variable synlib "synlib_optimize_non_cache_elements"#@ group_variable synlib "synlib_prefer_ultra_license"#@ group_variable synlib "synlib_sequential_module"#@ group_variable synlib "synlib_wait_for_design_license"#@ group_variable synlib "synthetic_library"#@#@ # "insert_dft" variables are used by the insert_dft and preview_dft commands#@ group_variable insert_dft "test_default_client_order"#@ group_variable insert_dft "test_point_keep_hierarchy"#@ group_variable insert_dft "insert_dft_clean_up"#@ group_variable insert_dft "insert_test_design_naming_style"#@ group_variable insert_dft "test_clock_port_naming_style"#@ group_variable insert_dft "test_default_min_fault_coverage"#@ group_variable insert_dft "test_scan_clock_a_port_naming_style"#@ group_variable insert_dft "test_scan_clock_b_port_naming_style"#@ group_variable insert_dft "test_scan_clock_port_naming_style"#@ group_variable insert_dft "test_scan_enable_inverted_port_naming_style"#@ group_variable insert_dft "test_scan_enable_port_naming_style"#@ group_variable insert_dft "test_scan_in_port_naming_style"#@ group_variable insert_dft "test_scan_out_port_naming_style"#@ group_variable insert_dft "test_non_scan_clock_port_naming_style"#@ group_variable insert_dft "test_dedicated_subdesign_scan_outs"#@ group_variable insert_dft "test_disable_find_best_scan_out"#@ group_variable insert_dft "test_dont_fix_constraint_violations"#@ group_variable insert_dft "test_isolate_hier_scan_out"#@ group_variable insert_dft "test_mode_port_naming_style"#@ group_variable insert_dft "test_mode_port_inverted_naming_style"#@ group_variable insert_dft "compile_dont_use_dedicated_scanout"#@ group_variable insert_dft "test_mux_constant_so"#@#@ # "preview_scan" variables are used by the preview_scan command#@ group_variable preview_scan "test_preview_scan_shows_cell_types"#@ group_variable preview_scan "test_scan_link_so_lockup_key"#@ group_variable preview_scan "test_scan_link_wire_key"#@ group_variable preview_scan "test_scan_segment_key"#@ group_variable preview_scan "test_scan_true_key"#@ group_variable preview_scan "test_jump_over_bufs_invs"#@#@ # "bsd" variables are used by the check_bsd and write_bsdl commands#@ group_variable bsd "test_user_test_data_register_naming_style"#@ group_variable bsd "test_user_defined_instruction_naming_style"#@ group_variable bsd "test_bsdl_default_suffix_name"#@ group_variable bsd "test_bsdl_max_line_length"#@ group_variable bsd "test_cc_ir_masked_bits"#@ group_variable bsd "test_cc_ir_value_of_masked_bits"#@#@ group_variable bsd "test_bsd_allow_tolerable_violations"#@ group_variable bsd "test_bsd_optimize_control_cell"#@ group_variable bsd "test_bsd_control_cell_drive_limit"#@ group_variable bsd "test_bsd_manufacturer_id"#@ group_variable bsd "test_bsd_part_number"#@ group_variable bsd "test_bsd_version_number"#@#@#@ # testmanager variables#@ group_variable testmanager "multi_pass_test_generation"#@#@ # "testsim" variables#@ # group_variable testsim "testsim_print_stats_file"#@#@ # "test" variables#@ group_variable test "test_default_bidir_delay"#@ group_variable test "test_default_delay"#@ group_variable test "test_default_period"#@ group_variable test "test_default_strobe"#@ group_variable test "test_default_strobe_width"#@ group_variable test "test_capture_clock_skew"#@ group_variable test "test_allow_clock_reconvergence"#@ group_variable test "test_default_scan_style"#@ group_variable test "test_check_port_changes_in_capture"#@ group_variable test "test_stil_netlist_format"#@ group_variable test "test_stil_multiclock_capture_procedures"#@ group_variable test "test_stil_max_line_length"#@ group_variable test "test_write_four_cycle_stil_protocol"#@ group_variable test "test_infer_slave_clock_pulse_after_capture"#@ group_variable test "test_protocol_add_cycle"#@ group_variable test "test_rtldrc_latch_check_style"#@#@ # "jtag" variables#@ group_variable jtag "jtag_manufacturer_id"#@ group_variable jtag "jtag_part_number"#@ group_variable jtag "jtag_port_drive_limit"#@ group_variable jtag "jtag_version_number"#@ group_variable jtag "jtag_test_data_in_port_naming_style"#@ group_variable jtag "jtag_test_data_out_port_naming_style"#@ group_variable jtag "jtag_test_mode_select_port_naming_style"#@#@ group_variable jtag "jtag_test_clock_port_naming_style"#@ group_variable jtag "jtag_test_reset_port_naming_style"#@#@ # "atpg" variables are used by the create_test_patterns command#@ # From Peace on, the "atpg_test_asynchronous_pins" is obsolete#@ # group_variable atpg "atpg_test_asynchronous_pins"#@ group_variable atpg "atpg_bidirect_output_only"#@#@ # "write_test" variables are used by the write_test command#@ group_variable write_test "write_test_formats"#@ group_variable write_test "write_test_include_scan_cell_info"#@ group_variable write_test "write_test_input_dont_care_value"#@ group_variable write_test "write_test_max_cycles"#@ group_variable write_test "write_test_max_scan_patterns"#@ group_variable write_test "write_test_pattern_set_naming_style"#@ group_variable write_test "write_test_scan_check_file_naming_style"#@ group_variable write_test "write_test_vector_file_naming_style"#@ group_variable write_test "write_test_round_timing_values"#@#@ # "schematic" variables are used by the create_schematic command#@ group_variable schematic "bus_dimension_separator_style"#@ group_variable schematic "bus_naming_style"#@ group_variable schematic "bus_range_separator_style"#@ group_variable schematic "duplicate_ports"#@ group_variable schematic "generic_symbol_library"#@ group_variable schematic "gen_max_ports_on_symbol_side"#@ group_variable schematic "gen_bussing_exact_implicit"#@ group_variable schematic "gen_cell_pin_name_separator"#@ group_variable schematic "gen_max_compound_name_length"#@ group_variable schematic "single_group_per_sheet"#@ group_variable schematic "symbol_library"#@ group_variable schematic "use_port_name_for_oscs"#@ group_variable schematic "default_schematic_options"#@ group_variable schematic "gen_match_ripper_wire_widths"#@ group_variable schematic "gen_show_created_busses"#@ group_variable schematic "gen_show_created_symbols"#@ group_variable schematic "gen_dont_show_single_bit_busses"#@ group_variable schematic "gen_single_osc_per_name"#@ group_variable schematic "gen_create_netlist_busses"#@ group_variable schematic "gen_open_name_prefix"#@ group_variable schematic "gen_open_name_postfix"#@ group_variable schematic "sort_outputs"#@#@ # "view" variables are used by the design_analyzer#@ group_variable view "x11_set_cursor_background"#@ group_variable view "x11_set_cursor_foreground"#@ group_variable view "x11_set_cursor_number"#@#@#@ if { [info exists x11_is_color] } {#@ if { $x11_is_color != "x11_is_color"} {#@ group_variable view "x11_is_color"#@ group_variable view "x11_display_string"#@ group_variable view "x11_vendor_version_number"#@ group_variable view "x11_vendor_release_number"#@ group_variable view "x11_vendor_string"#@ }#@ }#@#@ group_variable view "default_schematic_options"#@ group_variable view "view_arch_types"#@ group_variable view "view_background"#@ group_variable view "view_command_log_file"#@ group_variable view "view_dialogs_modal"#@ group_variable view "view_disable_cursor_warping"#@ group_variable view "view_disable_error_windows"#@ group_variable view "view_error_window_count"#@ group_variable view "view_log_file"#@ group_variable view "view_use_x_routines"#@ group_variable view "view_cache_images"#@ group_variable view "view_disable_output"#@ group_variable view "view_command_win_max_lines"#@ group_variable view "view_on_line_doc_cmd"#@ group_variable view "view_info_search_cmd"#@ group_variable view "view_script_submenu_items"#@ group_variable view "view_use_small_cursor"#@#@ # These next variable are also in the `suffix' group#@ group_variable view "view_execute_script_suffix"#@ group_variable view "view_read_file_suffix"#@ group_variable view "view_analyze_file_suffix"#@ group_variable view "view_write_file_suffix"#@#@ # group the text viewer variable with the other Design Analyzer variables.#@ group_variable view "text_editor_command"#@ group_variable view "text_print_command"#@#@ group_variable view "view_tools_menu_items"#@#@ group_variable view "test_design_analyzer_uses_insert_scan"#@#@ if { ( [string compare $synopsys_program_name "design_vision"] == 0 ) ||#@ ( [string compare $synopsys_program_name "psyn_gui"] == 0 ) } {#@ group_variable view "dv_enable_conservative_invalidate"#@ }#@#@ # "io" variables are used by the read, read_lib, db2sge and write commands#@ group_variable io "bus_inference_descending_sort"#@ group_variable io "bus_inference_style"#@ group_variable io "db2sge_output_directory"#@ group_variable io "db2sge_scale"#@ group_variable io "db2sge_overwrite"#@ group_variable io "db2sge_display_symbol_names"#@ group_variable io "db2sge_display_pin_names"#@ group_variable io "db2sge_display_instance_names"#@ group_variable io "db2sge_use_bustaps"#@ group_variable io "db2sge_use_compound_names"#@ group_variable io "db2sge_bit_type"#@ group_variable io "db2sge_bit_vector_type"#@ group_variable io "db2sge_one_name"#@ group_variable io "db2sge_zero_name"#@ group_variable io "db2sge_unknown_name"#@ group_variable io "db2sge_target_xp"#@ group_variable io "db2sge_tcf_package_file"#@ group_variable io "db2sge_use_lib_section"#@ group_variable io "db2sge_script"#@ group_variable io "db2sge_command"#@ group_variable io "equationout_and_sign"#@ group_variable io "equationout_or_sign"#@ group_variable io "equationout_postfix_negation"#@ group_variable io "lsiin_net_name_prefix"#@ group_variable io "lsiout_inverter_cell"#@ group_variable io "lsiout_upcase"#@ group_variable io "mentor_bidirect_value"#@ group_variable io "mentor_do_path"#@ group_variable io "mentor_input_output_property_name"#@ group_variable io "mentor_input_value"#@ group_variable io "mentor_logic_one_value"#@ group_variable io "mentor_logic_zero_one_property_name"#@ group_variable io "mentor_logic_zero_value"#@ group_variable io "mentor_output_value"#@ group_variable io "mentor_primitive_property_name"#@ group_variable io "mentor_primitive_property_value"#@ group_variable io "mentor_reference_property_name"#@ group_variable io "mentor_search_path"#@ group_variable io "mentor_write_symbols"#@ group_variable io "pla_read_create_flip_flop"#@ group_variable io "tdlout_upcase"#@ group_variable io "write_name_nets_same_as_ports"#@ group_variable io "xnfout_constraints_per_endpoint"#@ group_variable io "xnfout_default_time_constraints"#@ group_variable io "xnfout_clock_attribute_style"#@ group_variable io "xnfout_library_version"#@ group_variable io "xnfin_family"#@ group_variable io "xnfin_ignore_pins"#@ group_variable io "xnfin_dff_reset_pin_name"#@ group_variable io "xnfin_dff_set_pin_name"#@ group_variable io "xnfin_dff_clock_enable_pin_name"#@ group_variable io "xnfin_dff_data_pin_name"#@ group_variable io "xnfin_dff_clock_pin_name" ;#@ group_variable io "xnfin_dff_q_pin_name";#@ group_variable io "sdfin_min_rise_net_delay" ;#@ group_variable io "sdfin_min_fall_net_delay" ;#@ group_variable io "sdfin_min_rise_cell_delay" ;#@ group_variable io "sdfin_min_fall_cell_delay" ;#@ group_variable io "sdfin_rise_net_delay_type" ;#@ group_variable io "sdfin_fall_net_delay_type" ;#@ group_variable io "sdfin_rise_cell_delay_type" ;#@ group_variable io "sdfin_fall_cell_delay_type" ;#@ group_variable io "sdfin_top_instance_name" ;#@ group_variable io "sdfout_time_scale" ;#@ group_variable io "sdfout_write_to_output" ;#@ group_variable io "sdfout_top_instance_name" ;#@ group_variable io "sdfout_min_rise_net_delay" ;#@ group_variable io "sdfout_min_fall_net_delay" ;#@ group_variable io "sdfout_min_rise_cell_delay" ;#@ group_variable io "sdfout_min_fall_cell_delay" ;#@ group_variable io "read_db_lib_warnings" ;#@ group_variable io "read_translate_msff" ;#@ group_variable io "libgen_max_differences" ;#@ group_variable io "read_name_mapping_nowarn_libraries" ;#@ group_variable io "write_name_mapping_nowarn_libraries" ;#@#@#@ # "edif" variables are used by the EDIF format read, read_lib, write,#@ # and write_lib commands#@ group_variable edif "bus_dimension_separator_style" ;#@ group_variable edif "bus_extraction_style" ;#@ group_variable edif "bus_inference_descending_sort" ;#@ group_variable edif "bus_inference_style" ;#@ group_variable edif "bus_naming_style" ;#@ group_variable edif "bus_range_separator_style" ;#@ group_variable edif "edifin_autoconnect_offpageconnectors" ;#@ group_variable edif "edifin_autoconnect_ports" ;#@ group_variable edif "edifin_delete_empty_cells" ;#@ group_variable edif "edifin_delete_ripper_cells" ;#@ group_variable edif "edifin_ground_net_name" ;#@ group_variable edif "edifin_ground_net_property_name" ;#@ group_variable edif "edifin_ground_net_property_value" ;#@ group_variable edif "edifin_ground_port_name" ;#@ group_variable edif "edifin_instance_property_name" ;#@ group_variable edif "edifin_portinstance_disabled_property_name" ;#@ group_variable edif "edifin_portinstance_disabled_property_value" ;#@ group_variable edif "edifin_portinstance_property_name" ;#@ group_variable edif "edifin_power_net_name" ;#@ group_variable edif "edifin_power_net_property_name" ;#@ group_variable edif "edifin_power_net_property_value" ;#@ group_variable edif "edifin_power_port_name" ;#@ group_variable edif "edifin_use_identifier_in_rename" ;#@ group_variable edif "edifin_view_identifier_property_name" ;#@ group_variable edif "edifin_dc_script_flag" ;#@ group_variable edif "edifin_lib_logic_1_symbol" ;#@ group_variable edif "edifin_lib_logic_0_symbol" ;#@ group_variable edif "edifin_lib_in_port_symbol" ;#@ group_variable edif "edifin_lib_out_port_symbol" ;#@ group_variable edif "edifin_lib_inout_port_symbol" ;#@ group_variable edif "edifin_lib_in_osc_symbol" ;#@ group_variable edif "edifin_lib_out_osc_symbol" ;#@ group_variable edif "edifin_lib_inout_osc_symbol" ;#@ group_variable edif "edifin_lib_mentor_netcon_symbol" ;#@ group_variable edif "edifin_lib_ripper_bits_property" ;#@ group_variable edif "edifin_lib_ripper_bus_end" ;#@ group_variable edif "edifin_lib_ripper_cell_name" ;#@ group_variable edif "edifin_lib_ripper_view_name" ;#@ group_variable edif "edifin_lib_route_grid" ;#@ group_variable edif "edifin_lib_templates" ;#@ group_variable edif "edifout_dc_script_flag" ;#@ group_variable edif "edifout_design_name" ;#@ group_variable edif "edifout_designs_library_name" ;#@ group_variable edif "edifout_display_instance_names" ;#@ group_variable edif "edifout_display_net_names" ;#@ group_variable edif "edifout_external" ;#@ group_variable edif "edifout_external_graphic_view_name" ;#@ group_variable edif "edifout_external_netlist_view_name" ;#@ group_variable edif "edifout_external_schematic_view_name" ;#@ group_variable edif "edifout_ground_name" ;#@ group_variable edif "edifout_ground_net_name" ;#@ group_variable edif "edifout_ground_net_property_name" ;#@ group_variable edif "edifout_ground_net_property_value" ;#@ group_variable edif "edifout_ground_pin_name" ;#@ group_variable edif "edifout_ground_port_name" ;#@ group_variable edif "edifout_instance_property_name" ;#@ group_variable edif "edifout_instantiate_ports" ;#@ group_variable edif "edifout_library_graphic_view_name" ;#@ group_variable edif "edifout_library_netlist_view_name" ;#@ group_variable edif "edifout_library_schematic_view_name" ;#@ group_variable edif "edifout_merge_libraries" ;#@ group_variable edif "edifout_multidimension_arrays" ;#@ group_variable edif "edifout_name_oscs_different_from_ports" ;#@ group_variable edif "edifout_name_rippers_same_as_wires" ;#@ group_variable edif "edifout_netlist_only" ;#@ group_variable edif "edifout_no_array" ;#@ group_variable edif "edifout_numerical_array_members" ;#@ group_variable edif "edifout_pin_direction_property_name" ;#@ group_variable edif "edifout_pin_direction_in_value" ;#@ group_variable edif "edifout_pin_direction_inout_value" ;#@ group_variable edif "edifout_pin_direction_out_value" ;#@ group_variable edif "edifout_pin_name_property_name" ;#@ group_variable edif "edifout_portinstance_disabled_property_name" ;#@ group_variable edif "edifout_portinstance_disabled_property_value" ;#@ group_variable edif "edifout_portinstance_property_name"#@ group_variable edif "edifout_power_and_ground_representation"#@ group_variable edif "edifout_power_name"#@ group_variable edif "edifout_power_net_name"#@ group_variable edif "edifout_power_net_property_name"#@ group_variable edif "edifout_power_net_property_value"#@ group_variable edif "edifout_power_pin_name"#@ group_variable edif "edifout_power_port_name"#@ group_variable edif "edifout_skip_port_implementations"#@ group_variable edif "edifout_target_system"#@ group_variable edif "edifout_top_level_symbol"#@ group_variable edif "edifout_translate_origin"#@ group_variable edif "edifout_unused_property_value"#@ group_variable edif "edifout_write_attributes"#@ group_variable edif "edifout_write_constraints"#@ group_variable edif "edifout_write_properties_list"#@ group_variable edif "write_name_nets_same_as_ports"#@#@ # "hdl" variables are variables pertaining to hdl reading and optimizing#@ group_variable hdl "bus_dimension_separator_style"#@ group_variable hdl "bus_minus_style"#@ group_variable hdl "bus_naming_style"#@ group_variable hdl "hdlin_advisor_directory"#@ group_variable hdl "design_library_file"#@ group_variable hdl "hdlin_enable_presto"#@ group_variable hdl "hdlin_infer_enumerated_types"#@ group_variable hdl "hdlin_optimize_enum_types"#@ group_variable hdl "hdlin_write_gtech_design_directory"#@ group_variable hdl "hdlin_enable_analysis_info"#@ group_variable hdl "hdlin_enable_analysis_info_for_analyze"#@ group_variable hdl "hdlin_hide_resource_line_numbers"#@ group_variable hdl "hdlin_auto_save_templates"#@ group_variable hdl "hdlin_replace_synthetic"#@ group_variable hdl "hdlin_latch_always_async_set_reset"#@ group_variable hdl "hdlin_ff_always_sync_set_reset"#@ group_variable hdl "hdlin_ff_always_async_set_reset"#@ group_variable hdl "hdlin_keep_feedback"#@ group_variable hdl "hdlin_keep_inv_feedback"#@ group_variable hdl "hdlin_check_no_latch"#@ group_variable hdl "hdlin_report_inferred_modules"#@ group_variable hdl "hdlin_reg_report_length"#@ group_variable hdl "hdlin_translate_off_skip_text"#@ group_variable hdl "hdlin_merge_nested_conditional_statements"#@ group_variable hdl "hdlin_infer_mux"#@ group_variable hdl "hdlin_dont_infer_mux_for_resource_sharing"#@ group_variable hdl "hdlin_mux_oversize_ratio"#@ group_variable hdl "hdlin_mux_size_limit"#@ group_variable hdl "hdlin_infer_multibit"#@ group_variable hdl "hdlin_enable_vpp"#@ group_variable hdl "hdlin_preserve_vpp_files"#@ group_variable hdl "hdlin_vpp_temporary_directory"#@ group_variable hdl "hdl_preferred_license"#@ group_variable hdl "hdl_keep_licenses"#@ group_variable hdl "hlo_resource_allocation"#@ group_variable hdl "hlo_transform_constant_multiplication"#@ group_variable hdl "hlo_minimize_tree_delay"#@ group_variable hdl "hlo_resource_implementation"#@ group_variable hdl "hlo_share_common_subexpressions"#@ group_variable hdl "hlo_share_effort"#@ group_variable hdl "hlo_ignore_priorities"#@ group_variable hdl "hdl_naming_threshold"#@ group_variable hdl "template_naming_style"#@ group_variable hdl "template_parameter_style"#@ group_variable hdl "template_separator_style"#@ group_variable hdl "verilogout_equation"#@ group_variable hdl "verilogout_ignore_case"#@ group_variable hdl "verilogout_no_tri"#@ group_variable hdl "verilogout_single_bit"#@ group_variable hdl "verilogout_higher_designs_first"#@ group_variable hdl "verilogout_levelize"#@ group_variable hdl "verilogout_include_files"#@ group_variable hdl "verilogout_unconnected_prefix"#@ group_variable hdl "verilogout_show_unconnected_pins"#@ group_variable hdl "verilogout_no_negative_index"#@ group_variable hdl "hdlin_dont_check_param_width"#@ group_variable hdl "hdlin_enable_rtldrc_info"#@#@ # "vhdlio" variables are variables pertaining to VHDL generation#@ group_variable vhdlio "vhdllib_timing_mesg"#@ group_variable vhdlio "vhdllib_timing_xgen"#@ group_variable vhdlio "vhdllib_timing_checks"#@ group_variable vhdlio "vhdllib_negative_constraint"#@ group_variable vhdlio "vhdllib_pulse_handle"#@ group_variable vhdlio "vhdllib_glitch_handle"#@ group_variable vhdlio "vhdllib_architecture"#@ group_variable vhdlio "vhdllib_tb_compare"#@ group_variable vhdlio "vhdllib_tb_x_eq_dontcare"#@ group_variable vhdlio "vhdllib_logic_system"#@ group_variable vhdlio "vhdllib_logical_name"#@#@ group_variable vhdlio "vhdlout_architecture_name"#@ group_variable vhdlio "vhdlout_bit_type"#@ group_variable vhdlio "vhdlout_bit_type_resolved"#@ group_variable vhdlio "vhdlout_bit_vector_type"#@ group_variable vhdlio "vhdlout_conversion_functions"#@ group_variable vhdlio "vhdlout_dont_write_types"#@ group_variable vhdlio "vhdlout_equations"#@ group_variable vhdlio "vhdlout_one_name"#@ group_variable vhdlio "vhdlout_package_naming_style"#@ group_variable vhdlio "vhdlout_preserve_hierarchical_types"#@ group_variable vhdlio "vhdlout_separate_scan_in"#@ group_variable vhdlio "vhdlout_single_bit"#@ group_variable vhdlio "vhdlout_target_simulator"#@ group_variable vhdlio "vhdlout_top_configuration_arch_name"#@ group_variable vhdlio "vhdlout_top_configuration_entity_name"#@ group_variable vhdlio "vhdlout_top_configuration_name"#@ group_variable vhdlio "vhdlout_three_state_name"#@ group_variable vhdlio "vhdlout_three_state_res_func"#@ group_variable vhdlio "vhdlout_time_scale"#@ group_variable vhdlio "vhdlout_unknown_name"#@ group_variable vhdlio "vhdlout_use_packages"#@ group_variable vhdlio "vhdlout_wired_and_res_func"#@ group_variable vhdlio "vhdlout_wired_or_res_func"#@ group_variable vhdlio "vhdlout_write_architecture"#@ group_variable vhdlio "vhdlout_write_entity"#@ group_variable vhdlio "vhdlout_write_top_configuration"#@ group_variable vhdlio "vhdlout_synthesis_off"#@ group_variable vhdlio "vhdlout_write_components"#@ group_variable vhdlio "vhdlout_zero_name"#@ group_variable vhdlio "vhdlout_levelize"#@ group_variable vhdlio "vhdlout_dont_create_dummy_nets"#@ group_variable vhdlio "vhdlout_follow_vector_direction"#@#@ # "plot" variables are used by the plot command and by#@ # the plotting function in the schematic viewer#@ ##@ group_variable plot "plot_box"#@ group_variable plot "plot_command"#@ group_variable plot "plot_orientation"#@ group_variable plot "plot_scale_factor"#@ group_variable plot "plotter_maxx"#@ group_variable plot "plotter_maxy"#@ group_variable plot "plotter_minx"#@ group_variable plot "plotter_miny"#@#@ # "suffix" variables are used to find the suffixes of different file types#@ group_variable suffix "view_execute_script_suffix"#@ group_variable suffix "view_read_file_suffix"#@ group_variable suffix "view_analyze_file_suffix"#@ group_variable suffix "view_write_file_suffix"#@#@ # "bc" variables are used by BC to control scheduling behavior#@ #group_variable bc {bc_preserved_functions_map_effort}#@ group_variable bc {bc_enable_analysis_info}#@ group_variable bc {bc_enable_chaining}#@ group_variable bc {bc_enable_multi_cycle}#@ group_variable bc {bc_time_all_sequential_op_bindings}#@ group_variable bc {bc_enable_speculative_execution}#@ group_variable bc {bc_fsm_coding_style}#@#@ group_variable bc {bc_allow_shared_memories}#@ group_variable bc {bc_chain_read_into_mem}#@ group_variable bc {bc_chain_read_into_oper}#@ # Ki-Seok: removed (Jan. 1999): group_variable bc {bc_connect_reset}#@ group_variable bc {bc_constrain_signal_memories}#@ group_variable bc {bc_detect_memory_accesses}#@ group_variable bc {bc_detect_array_accesses}#@ group_variable bc {bc_estimate_mux_input}#@ group_variable bc {bc_estimate_timing_effort}#@ # Ki-Seok: removed (Jan. 1999): group_variable bc {bc_no_reset_on_datapath}#@ group_variable bc {bc_report_filter}#@ # Ki-Seok: removed: group_variable bc {bc_clears_all_registers}#@ group_variable bc {bc_group_eql_logic}#@ group_variable bc {bc_group_index_logic}#@ group_variable bc {bc_use_registerfiles}#@#@ group_variable bc {vhdlout_debug_mode}#@ group_variable bc {verilogout_debug_mode}#@#@ # Ki-Seok: Added bc_synrtl variables.#@ group_variable bc {bc_synrtl_map_to_gtech}#@ group_variable bc {bc_synrtl_write_precompiled_designware}#@ group_variable bc {bc_synrtl_write_preserved_functions}#@ group_variable bc {bc_synrtl_write_dcsh_and_dctcl}#@#@ # Meenakshi: Added bc_add_io_trace variable.#@ group_variable bc {bc_add_io_trace}#@#@ # Meenakshi: Added new group scc (for SystemC compiler)#@ group_variable scc {systemcout_levelize}#@ group_variable scc {systemcout_debug_mode}#@#@ # "power" variables are for power-analysis.#@ group_variable power {power_keep_license_after_power_commands}#@ group_variable power {power_preserve_rtl_hier_names}#@ group_variable power {power_do_not_size_icg_cells}#@ group_variable power {power_hdlc_do_not_split_cg_cells}#@ group_variable power {power_rtl_saif_file}#@ group_variable power {power_sdpd_saif_file}#@#@ # dpcm variables are used by DPCM lib and controllong DC when using DPCM#@#@ if { [info exists dpcm_debuglevel] } {#@ group_variable dpcm "dpcm_debuglevel"#@ group_variable dpcm "dpcm_rulespath"#@ group_variable dpcm "dpcm_rulepath"#@ group_variable dpcm "dpcm_tablepath"#@ group_variable dpcm "dpcm_libraries"#@ group_variable dpcm "dpcm_version"#@ group_variable dpcm "dpcm_level"#@ group_variable dpcm "dpcm_temperaturescope"#@ group_variable dpcm "dpcm_voltagescope"#@ group_variable dpcm "dpcm_functionscope"#@ group_variable dpcm "dpcm_wireloadscope"#@ group_variable dpcm "dpcm_slewlimit"#@ group_variable dpcm "dpcm_arc_sense_mapping"#@#@ }#@#@ set dpcm_slewlimit "TRUE"#@#@ # executable to fire off RTLA/BCV#@ group_variable hdl {xterm_executable}#@ group_variable bc {xterm_executable}#@#@ # Variable group for Chip Compiler#@ if {[info exists acs_work_dir]} {#@ group_variable acs acs_work_dir#@ group_variable acs acs_hdl_source#@ group_variable acs acs_verilog_extensions#@ group_variable acs acs_vhdl_extensions#@ group_variable acs acs_exclude_extensions#@ group_variable acs acs_exclude_list#@ group_variable acs acs_area_report_suffix#@ group_variable acs acs_budgeted_cstr_suffix#@ group_variable acs acs_compile_script_suffix#@ group_variable acs acs_constraint_file_suffix#@ group_variable acs acs_cstr_report_suffix#@ group_variable acs acs_db_suffix#@ group_variable acs acs_log_file_suffix#@ group_variable acs acs_makefile_name#@ group_variable acs acs_override_script_suffix#@ group_variable acs acs_override_report_suffix#@ group_variable acs acs_qor_report_suffix#@ group_variable acs acs_timing_report_suffix#@ group_variable acs acs_user_compile_strategy_script_suffix#@ group_variable acs acs_global_user_compile_strategy_script#@ group_variable acs acs_budget_script_file_suffix#@ group_variable acs acs_budget_output_file_suffix#@ group_variable acs acs_use_lsf#@ group_variable acs acs_script_mode#@ group_variable acs acs_num_parallel_jobs#@ group_variable acs acs_user_budgeting_script#@ group_variable acs acs_bs_exec#@ group_variable acs acs_tr_exec#@ group_variable acs acs_dc_exec#@ group_variable acs acs_use_default_delays#@ group_variable acs acs_use_dc_gate_level_budgeting#@ group_variable acs acs_use_autopartition#@ group_variable acs check_error_list#@ }#@#@ # eco group includes variables related to ECO Compiler#@ group_variable eco "eco_align_design_verbose"#@ group_variable eco "eco_allow_register_type_difference"#@ group_variable eco "eco_connect_resource_cell_inputs"#@ group_variable eco "eco_correspondence_analysis_verbose"#@ group_variable eco "eco_directives_verbose"#@ group_variable eco "eco_implement_effort_level"#@ group_variable eco "eco_instance_name_prefix"#@ group_variable eco "eco_recycle_verbose"#@ group_variable eco "eco_remap_register_verbose"#@ group_variable eco "eco_reuse_verbose"#@#@ # Aliases for backwards compatibility or other reasons#@ group_variable compile {compile_log_format}#@ alias view_cursor_number x11_set_cursor_number#@ alias set_internal_load set_load#@ alias set_internal_arrival set_arrival#@ alias set_connect_delay "set_annotated_delay -net"#@ alias create_test_vectors create_test_patterns#@ alias compile_test insert_test#@ alias check_clocks check_timing#@ alias lint check_design#@ alias verify compare_design#@ alias gen create_schematic#@ alias free remove_design#@ alias group_bus create_bus#@ alias ungroup_bus remove_bus#@ alias groupvar group_variable#@ alias report_constraints report_constraint#@ alias report_attributes report_attribute#@ alias fsm_reduce reduce_fsm#@ alias fsm_minimize minimize_fsm#@ alias disable_timing set_disable_timing#@ alias dont_touch set_dont_touch#@ alias dont_touch_network set_dont_touch_network#@ alias dont_use set_dont_use#@ alias fix_hold set_fix_hold#@ alias prefer set_prefer#@ alias remove_package "echo remove_package command is obsolete: packages are stored on disk not in-memory:"#@ alias analyze_scan preview_scan#@#@ # Enable unsupported psyn commands#@ if { $synopsys_program_name == "psyn_shell" } {#@ proc enable_unsupported_commands { { arg "default" } } {#@ global cgpi_use_new_wire_factors#@ global cgpi_use_relative_wire_factors#@ global cgpi_use_new_path_factors#@ global pwlm_use_new_wire_factors#@ global pwlm_use_relative_wire_factors#@ global pwlm_use_new_path_factors#@ global psyn_unsupported_commands_dir#@ global synopsys_root#@ if {![info exists psyn_unsupported_commands_dir]} {#@ set psyn_unsupported_commands_dir $synopsys_root/auxx/syn/psyn/unsupported_commands#@ }#@ set psyn_unsupported_commands_option1 $arg#@ if {[file readable $psyn_unsupported_commands_dir/setup.tcl]} {#@ source $psyn_unsupported_commands_dir/setup.tcl#@ } else {#@ source -encrypted $psyn_unsupported_commands_dir/setup.tcl.e#@ }#@ }#@ }#@#@#@ # The ls command is gone, now it is just an alias for dc_shell eqn mode#@#@ if { [string compare $dc_shell_mode "default"] == 0 } {#@ if { ( $sh_arch == {mips}) && ( ( $synopsys_program_name == {design_analyzer}) || ( $isatty == 0)) } {#@ alias ls "sh ls -a "#@ } else {#@ if { ( $sh_arch == {mips}) || ( $sh_arch == {necmips}) } {#@ alias ls "sh ls -aC "#@ } else {#@ alias ls "sh ls -aC "#@ }#@ }#@ }#@#@ #/* Aliases added for report command */#@ alias report_clock_constraint "report_timing -path end -to all_registers(-data_pins)"#@ alias report_clock_fanout "report_transitive_fanout -clock_tree"#@ alias report_clocks report_clock#@ alias report_register "report_timing_requirements;report_clock -skew"#@ alias report_synthetic report_cell#@#@ # Alias added for Ultra backward compatibility mode#@ alias set_ultra_mode set_ultra_optimization#@#@ # alias for write_sge and menu item in DA for db2sge#@#@ if { [string compare $dc_shell_mode "tcl"] == 0 } {#@ set db2sge_script ${synopsys_root}/admin/setup/.dc_write_sge.tcl#@ } else {#@ set db2sge_script ${synopsys_root}/admin/setup/.dc_write_sge#@ }#@#@ set db2sge_command ${synopsys_root}/${sh_arch}/syn/bin/db2sge#@#@ #Don't change the view_script_submenu_items to make it work for both modes.#@ # fix star 107079 by "DA to SGE Transfer" from menu -- sherwood 07/27/00#@ if { $synopsys_program_name != "design_vision" && $synopsys_program_name != "psyn_gui" } {#@ set view_script_submenu_items "\"DA to SGE Transfer\" write_sge"#@ }#@#@#@ # read schematic annotation setup file#@ source ${synopsys_root}/admin/setup/.dc_annotate#@ annotate -value "@name" -object_type CELL -layer cell_name_layer -x "ANN_LEFT / 2 + ANN_RIGHT / 2" -y "ANN_TOP / 2 + ANN_BOTTOM / 2 - ANN_MAX_TEXT_HEIGHT" -name "cell_name" -justify "CENTER"#@#@ annotate -value "ANN_CELL_REF_NAME" -object_type CELL -layer cell_ref_name_layer -x "ANN_LEFT / 2 + ANN_RIGHT / 2" -y "ANN_TOP / 2 + ANN_BOTTOM / 2" -name "cell_ref_name" -justify "CENTER"#@#@ annotate -value "@cell_property" -object_type CELL -layer cell_property_layer -x "ANN_LEFT / 2 + ANN_RIGHT / 2" -y "ANN_TOP / 2 + ANN_BOTTOM / 2 + ANN_MAX_TEXT_HEIGHT" -name "cell_property" -justify "CENTER"#@#@ annotate -value "ANN_PORT_NAME" -object_type PORT -layer port_name_layer -filter "ANN_ROTATION == \"RIGHT\"" -x "ANN_RIGHT + ANN_ROUTE_GRID / 2" -y "ANN_TOP / 2 + ANN_BOTTOM / 2 - ANN_MAX_TEXT_HEIGHT / 2" -name "port_name_right"#@#@ annotate -value "ANN_PORT_NAME" -object_type PORT -layer port_name_layer -filter "ANN_ROTATION == \"LEFT\"" -x "ANN_LEFT - ANN_ROUTE_GRID / 2" -y "ANN_TOP / 2 + ANN_BOTTOM / 2 - ANN_MAX_TEXT_HEIGHT / 2" -name "port_name_left" -justify "RIGHT"#@#@ annotate -value "ANN_PORT_NAME" -object_type BUS_PORT -layer bus_port_name_layer -filter "ANN_ROTATION == \"RIGHT\"" -x "ANN_RIGHT + ANN_ROUTE_GRID / 2" -y "ANN_TOP / 2 + ANN_BOTTOM / 2 - ANN_MAX_TEXT_HEIGHT / 2" -name "bus_port_name_right"#@#@ annotate -value "ANN_PORT_NAME" -object_type BUS_PORT -layer bus_port_name_layer -filter "ANN_ROTATION == \"LEFT\"" -x "ANN_LEFT - ANN_ROUTE_GRID / 2" -y "ANN_TOP / 2 + ANN_BOTTOM / 2 - ANN_MAX_TEXT_HEIGHT / 2" -name "bus_port_name_left" -justify "RIGHT"#@#@ annotate -value "ANN_OSC_NAME" -object_type OSC -layer osc_name_layer -filter "ANN_ROTATION == \"RIGHT\"" -x "ANN_RIGHT + ANN_ROUTE_GRID / 2" -y "ANN_TOP / 2 + ANN_BOTTOM / 2 - ANN_MAX_TEXT_HEIGHT / 2" -name "osc_name_right"#@#@ annotate -value "ANN_OSC_NAME" -object_type OSC -layer osc_name_layer -filter "ANN_ROTATION == \"LEFT\"" -x "ANN_LEFT - ANN_ROUTE_GRID / 2" -y "ANN_TOP / 2 + ANN_BOTTOM / 2 - ANN_MAX_TEXT_HEIGHT / 2" -name "osc_name_left" -justify "RIGHT"#@#@ annotate -value "ANN_OSC_NAME" -object_type BUS_OSC -layer bus_osc_name_layer -filter "ANN_ROTATION == \"RIGHT\"" -x "ANN_RIGHT + ANN_ROUTE_GRID / 2" -y "ANN_TOP / 2 + ANN_BOTTOM / 2 - ANN_MAX_TEXT_HEIGHT / 2" -name "bus_osc_name_right"#@#@ annotate -value "ANN_OSC_NAME" -object_type BUS_OSC -layer bus_osc_name_layer -filter "ANN_ROTATION == \"LEFT\"" -x "ANN_LEFT - ANN_ROUTE_GRID / 2" -y "ANN_TOP / 2 + ANN_BOTTOM / 2 - ANN_MAX_TEXT_HEIGHT / 2" -name "bus_osc_name_left" -justify "RIGHT"#@#@ annotate -value "ANN_PIN_NAME" -object_type PIN -layer pin_name_layer -filter "ANN_ROTATION == \"RIGHT\" && ANN_IS_RIPPER_CELL == \"FALSE\"" -x "ANN_MAX_TEXT_WIDTH / 5" -y "ANN_MAX_TEXT_HEIGHT / 5" -name "pin_name_right"#@#@ annotate -value "ANN_PIN_NAME" -object_type PIN -layer pin_name_layer -filter "ANN_ROTATION == \"LEFT\" && ANN_IS_RIPPER_CELL == \"FALSE\"" -x "ANN_MAX_TEXT_WIDTH / 5" -y "- ANN_MAX_TEXT_HEIGHT / 2" -name "pin_name_left"#@#@ annotate -value "ANN_PIN_NAME" -object_type PIN -layer ripper_pin_name_layer -filter "ANN_ROTATION == \"RIGHT\" && ANN_IS_RIPPER_CELL == \"TRUE\"" -x "ANN_MAX_TEXT_WIDTH / 5" -y "ANN_MAX_TEXT_HEIGHT / 5" -name "ripper_pin_name_right"#@#@ annotate -value "ANN_PIN_NAME" -object_type PIN -layer ripper_pin_name_layer -filter "ANN_ROTATION == \"LEFT\" && ANN_IS_RIPPER_CELL == \"TRUE\"" -x "ANN_MAX_TEXT_WIDTH / 5" -y "- ANN_MAX_TEXT_HEIGHT / 2" -name "ripper_pin_name_left"#@#@ annotate -value "@pin_properties" -object_type PIN -layer pin_properties_layer -x "- ANN_MAX_TEXT_WIDTH / 5" -y "ANN_MAX_TEXT_HEIGHT / 5" -justify "RIGHT" -name "pin_properties"#@#@ annotate -value "ANN_PIN_NAME" -object_type BUS_PIN -layer bus_pin_name_layer -filter "ANN_ROTATION == \"RIGHT\"" -x "ANN_MAX_TEXT_WIDTH / 5" -y "ANN_MAX_TEXT_HEIGHT / 5" -name "bus_pin_name_right"#@#@ annotate -value "ANN_PIN_NAME" -object_type BUS_PIN -layer bus_pin_name_layer -filter "ANN_ROTATION == \"LEFT\"" -x "ANN_MAX_TEXT_WIDTH / 5" -y "- ANN_MAX_TEXT_HEIGHT / 2" -name "bus_pin_name_left"#@#@ annotate -value "ANN_RIPPER_NAME" -object_type RIPPER -layer bus_ripper_name_layer -y "ANN_BOTTOM - ANN_MAX_TEXT_HEIGHT" -name "ripper_name" -justify "CENTER"#@ # -- End source /usr/synopsys/synthesis/admin/setup/.dc_annotate#@#@ # setup the default layer settings#@ source ${synopsys_root}/admin/setup/.dc_layers#@ set_layer designware_layer line_width 400 ;#@ set_layer designware_layer line_max 4 ;#@ set_layer designware_layer scalable_lines true ;#@ set_layer designware_layer red 65535 ;#@ set_layer designware_layer green 0 ;#@ set_layer designware_layer blue 0 ;#@ set_layer designware_name_layer red 65535 ;#@ set_layer designware_name_layer green 65535 ;#@ set_layer designware_name_layer blue 65535 ;#@ set_layer designware_name_layer visible true ;#@#@ set_layer hierarchy_layer line_width 2 ;#@ set_layer cell_layer line_width 200 ;#@ set_layer bus_cell_layer line_width 400 ;#@ set_layer symbol_layer line_width 200 ;#@ set_layer bus_ripper_layer line_width 200 ;#@ set_layer osc_layer line_width 200 ;#@ set_layer port_layer line_width 200 ;#@ set_layer bus_osc_layer line_width 400 ;#@ set_layer bus_port_layer line_width 400 ;#@ set_layer cell_layer line_max 3 ;#@ set_layer bus_cell_layer line_max 4 ;#@ set_layer bus_cell_layer line_min 2 ;#@ set_layer symbol_layer line_max 3 ;#@ set_layer bus_ripper_layer line_max 3 ;#@ set_layer osc_layer line_max 2 ;#@ set_layer port_layer line_max 2 ;#@ set_layer bus_osc_layer line_max 4 ;#@ set_layer bus_port_layer line_max 4 ;#@ set_layer bus_osc_layer line_min 2 ;#@ set_layer bus_port_layer line_min 2 ;#@ set_layer net_layer line_width 1 ;#@ set_layer bus_net_layer line_width 3 ;#@#@ set_layer hierarchy_layer scalable_lines false ;#@ set_layer cell_layer scalable_lines true ;#@ set_layer bus_cell_layer scalable_lines true ;#@ set_layer symbol_layer scalable_lines true ;#@ set_layer bus_ripper_layer scalable_lines true ;#@ set_layer osc_layer scalable_lines true ;#@ set_layer port_layer scalable_lines true ;#@ set_layer bus_osc_layer scalable_lines true ;#@ set_layer bus_port_layer scalable_lines true ;#@ set_layer net_layer scalable_lines false ;#@ set_layer bus_net_layer scalable_lines false ;#@#@ set_layer template_layer scalable_lines false ;#@ set_layer template_layer line_width 3 ;#@ set_layer template_layer red 0 ;#@ set_layer template_layer green 45875 ;#@ set_layer template_layer blue 45875 ;#@ set_layer template_text_layer green 65535 ;#@ set_layer template_text_layer red 65535 ;#@ set_layer template_text_layer blue 65535 ;#@#@ set_layer net_layer red 0 ;#@ set_layer net_layer green 65535 ;#@ set_layer net_layer blue 65535 ;#@ set_layer bus_net_layer red 0 ;#@ set_layer bus_net_layer green 38666 ;#@ set_layer bus_net_layer blue 65535 ;#@ set_layer net_name_layer red 65535 ;#@ set_layer net_name_layer green 65535 ;#@ set_layer net_name_layer blue 65535 ;#@ set_layer symbol_name_layer red 65535 ;#@ set_layer symbol_name_layer green 65535 ;#@ set_layer symbol_name_layer blue 65535 ;#@ set_layer hierarchy_name_layer red 65535 ;#@ set_layer hierarchy_name_layer green 65535 ;#@ set_layer hierarchy_name_layer blue 65535 ;#@ set_layer bus_osc_name_layer red 65535 ;#@ set_layer bus_osc_name_layer green 65535 ;#@ set_layer bus_osc_name_layer blue 65535 ;#@ set_layer bus_port_name_layer red 65535 ;#@ set_layer bus_port_name_layer green 65535 ;#@ set_layer bus_port_name_layer blue 65535 ;#@ set_layer bus_cell_name_layer red 65535 ;#@ set_layer bus_cell_name_layer green 65535 ;#@ set_layer bus_cell_name_layer blue 65535 ;#@ set_layer bus_ripper_name_layer red 65535 ;#@ set_layer bus_ripper_name_layer green 65535 ;#@ set_layer bus_ripper_name_layer blue 65535 ;#@ set_layer bit_mapper_name_layer red 65535 ;#@ set_layer bit_mapper_name_layer green 65535 ;#@ set_layer bit_mapper_name_layer blue 65535 ;#@ set_layer bus_net_name_layer red 65535 ;#@ set_layer bus_net_name_layer green 65535 ;#@ set_layer bus_net_name_layer blue 65535 ;#@ set_layer bus_compound_name_layer red 65535 ;#@ set_layer bus_compound_name_layer green 65535 ;#@ set_layer bus_compound_name_layer blue 65535 ;#@ set_layer cell_layer red 65535 ;#@ set_layer cell_layer green 65535 ;#@ set_layer cell_layer blue 0 ;#@ set_layer bus_cell_layer red 0 ;#@ set_layer bus_cell_layer green 65535 ;#@ set_layer bus_cell_layer blue 65535 ;#@ set_layer hierarchy_layer red 65535 ;#@ set_layer hierarchy_layer green 65535 ;#@ set_layer hierarchy_layer blue 0 ;#@ set_layer symbol_layer red 65535 ;#@ set_layer symbol_layer green 65535 ;#@ set_layer symbol_layer blue 0 ;#@ set_layer bus_ripper_layer red 65535 ;#@ set_layer bus_ripper_layer green 65535 ;#@ set_layer bus_ripper_layer blue 0 ;#@ set_layer cell_ref_name_layer red 65535 ;#@ set_layer cell_ref_name_layer green 65535 ;#@ set_layer cell_ref_name_layer blue 65535 ;#@ set_layer cell_name_layer red 65535 ;#@ set_layer cell_name_layer green 65535 ;#@ set_layer cell_name_layer blue 65535 ;#@ set_layer port_layer red 65535 ;#@ set_layer port_layer green 65535 ;#@ set_layer port_layer blue 0 ;#@ set_layer bus_osc_layer red 65535 ;#@ set_layer bus_osc_layer green 65535 ;#@ set_layer bus_osc_layer blue 0 ;#@ set_layer bus_port_layer red 65535 ;#@ set_layer bus_port_layer green 65535 ;#@ set_layer bus_port_layer blue 0 ;#@ set_layer port_name_layer red 65535 ;#@ set_layer port_name_layer green 65535 ;#@ set_layer port_name_layer blue 65535 ;#@ set_layer pin_name_layer red 65535 ;#@ set_layer pin_name_layer green 65535 ;#@ set_layer pin_name_layer blue 65535 ;#@ set_layer ripper_pin_name_layer red 65535 ;#@ set_layer ripper_pin_name_layer green 65535 ;#@ set_layer ripper_pin_name_layer blue 65535 ;#@ set_layer bus_pin_name_layer red 65535 ;#@ set_layer bus_pin_name_layer green 65535 ;#@ set_layer bus_pin_name_layer blue 65535 ;#@ set_layer osc_layer red 65535 ;#@ set_layer osc_layer green 65535 ;#@ set_layer osc_layer blue 0 ;#@ set_layer osc_name_layer red 65535 ;#@ set_layer osc_name_layer green 65535 ;#@ set_layer osc_name_layer blue 65535 ;#@#@ set_layer bus_net_layer visible true ;#@ set_layer bus_compound_name_layer visible false ;#@ set_layer bus_net_name_layer visible false ;#@ set_layer bus_osc_layer visible true ;#@ set_layer bus_port_layer visible true ;#@ set_layer bus_osc_name_layer visible true ;#@ set_layer bus_port_name_layer visible true ;#@ set_layer bus_ripper_layer visible true ;#@ set_layer bus_ripper_name_layer visible true ;#@ set_layer bit_mapper_name_layer visible true ;#@ set_layer cell_layer visible true ;#@ set_layer cell_name_layer visible false ;#@ set_layer cell_ref_name_layer visible true ;#@ set_layer bus_cell_layer visible true ;#@ set_layer bus_cell_name_layer visible true ;#@ set_layer hierarchy_layer visible true ;#@ set_layer hierarchy_name_layer visible true ;#@ set_layer highlight_layer0 visible true ;#@ set_layer highlight_layer1 visible true ;#@ set_layer highlight_layer2 visible true ;#@ set_layer highlight_layer3 visible true ;#@ set_layer net_layer visible true ;#@ set_layer net_name_layer visible false ;#@ set_layer osc_layer visible true ;#@ set_layer osc_name_layer visible true ;#@ set_layer pin_name_layer visible false ;#@ set_layer ripper_pin_name_layer visible false ;#@ set_layer bus_pin_name_layer visible false ;#@ set_layer port_layer visible true ;#@ set_layer port_name_layer visible true ;#@ set_layer symbol_layer visible true ;#@ set_layer symbol_name_layer visible true ;#@ set_layer template_layer visible true ;#@ set_layer template_text_layer visible true ;#@ set_layer variable_layer visible false ;#@#@ set_layer constraint_layer line_width 50 ;#@ set_layer constraint_layer line_max 3 ;#@ set_layer constraint_layer scalable_lines true ;#@ set_layer constraint_layer red 65535 ;#@ set_layer constraint_layer green 0 ;#@ set_layer constraint_layer blue 0 ;#@ set_layer constraint_layer visible true ;#@#@ set_layer clock_layer line_width 50 ;#@ set_layer clock_layer line_max 3 ;#@ set_layer clock_layer scalable_lines true ;#@ set_layer clock_layer red 65535 ;#@ set_layer clock_layer green 0 ;#@ set_layer clock_layer blue 0 ;#@ set_layer clock_layer visible true ;#@#@#@ #/* The highlight layers are set up differently depending on if we're color */#@ if { [info exists x11_is_color] } {#@ if { $x11_is_color == "true"} {#@#@ # /* red */#@ set_layer highlight_layer0 visible true ;#@ set_layer highlight_layer0 line_width 5 ;#@ set_layer highlight_layer0 scalable_lines false ;#@ set_layer highlight_layer0 red 65535 ;#@ set_layer highlight_layer0 green 0 ;#@ set_layer highlight_layer0 blue 0 ;#@ set_layer highlight_layer0 plot_line_width 10 ;#@#@ # /* green */#@ set_layer highlight_layer1 visible true ;#@ set_layer highlight_layer1 line_width 5 ;#@ set_layer highlight_layer1 scalable_lines false ;#@ set_layer highlight_layer1 red 0 ;#@ set_layer highlight_layer1 green 65535 ;#@ set_layer highlight_layer1 blue 0 ;#@ set_layer highlight_layer1 plot_line_width 10 ;#@#@ # /* magenta */#@ set_layer highlight_layer2 visible true ;#@ set_layer highlight_layer2 line_width 5 ;#@ set_layer highlight_layer2 scalable_lines false ;#@ set_layer highlight_layer2 red 65535 ;#@ set_layer highlight_layer2 green 0 ;#@ set_layer highlight_layer2 blue 65535 ;#@ set_layer highlight_layer2 plot_line_width 10 ;#@#@ # /* flesh */#@ set_layer highlight_layer3 visible true ;#@ set_layer highlight_layer3 line_width 5 ;#@ set_layer highlight_layer3 scalable_lines false ;#@ set_layer highlight_layer3 red 65535 ;#@ set_layer highlight_layer3 green 50462 ;#@ set_layer highlight_layer3 blue 35389 ;#@ set_layer highlight_layer3 plot_line_width 10 ;#@#@ # /* yellow */#@ set_layer highlight_layer4 visible true ;#@ set_layer highlight_layer4 line_width 5 ;#@ set_layer highlight_layer4 scalable_lines false ;#@ set_layer highlight_layer4 red 62258 ;#@ set_layer highlight_layer4 green 65535 ;#@ set_layer highlight_layer4 blue 0 ;#@ set_layer highlight_layer4 plot_line_width 10 ;#@#@#@ } else {#@#@ set_layer highlight_layer0 line_width 5 ;#@ set_layer highlight_layer0 scalable_lines false ;#@ set_layer highlight_layer0 red 65535 ;#@ set_layer highlight_layer0 green 0 ;#@ set_layer highlight_layer0 blue 0 ;#@ set_layer highlight_layer0 plot_line_width 10 ;#@#@ set_layer highlight_layer1 line_width 3 ;#@ set_layer highlight_layer1 scalable_lines false ;#@ set_layer highlight_layer1 red 0 ;#@ set_layer highlight_layer1 green 65535 ;#@ set_layer highlight_layer1 blue 0 ;#@ set_layer highlight_layer1 plot_line_width 10 ;#@#@ set_layer highlight_layer2 line_width 5 ;#@ set_layer highlight_layer2 scalable_lines false ;#@ set_layer highlight_layer2 red 65535 ;#@ set_layer highlight_layer2 green 0 ;#@ set_layer highlight_layer2 blue 0 ;#@ set_layer highlight_layer2 plot_line_width 10 ;#@#@ set_layer highlight_layer3 line_width 3 ;#@ set_layer highlight_layer3 scalable_lines false ;#@ set_layer highlight_layer3 red 0 ;#@ set_layer highlight_layer3 green 65535 ;#@ set_layer highlight_layer3 blue 0 ;#@ set_layer highlight_layer3 plot_line_width 10 ;#@#@ }#@ }#@#@ # -- End source /usr/synopsys/synthesis/admin/setup/.dc_layers#@#@#@ source ${synopsys_root}/admin/setup/.dc_name_rules#@ ##@#@ # .dc_name_rules Initialization file for#@#@ # Dc_Shell and Design_Analyzer#@#@ # This files defines name rules for target systems. Change_names#@ # will use this rules to fix the object names.#@#@ #*/#@#@ ###/* Name rule for SGE */#@#@ define_name_rules sge -special sge -replacement_char "x"#@ define_name_rules sge -type net -allowed {A-Z a-z _ 0-9 \[\](){}~!@#%^&*+?/}#@ define_name_rules sge -type port -allowed {A-Z a-z _ 0-9 \[\](){}~!@#%^&*+?/}#@ define_name_rules sge -type cell -allowed "A-Z a-z _ 0-9~!@#%^&*+?/$-" -first_restricted "_" -last_restricted "_"#@#@ ###/* Name rule for SGE and VHDL */#@#@ define_name_rules sge_vhdl -reserved_words { "abs" "access" "after" "alias" "all" "and" "architecture" "array" "assert" "attribute" "begin" "block" "body" "buffer" "bus" "case" "component" "configuration" "constant" "disconnect" "downto" "else" "elsif" "end" "entity" "exit" "file" "for" "function" "generate" "generic" "group" "guarded" "if" "impure" "in" "inertial" "inout" "is" "label" "library" "linkage" "literal" "loop" "map" "mod" "nand" "new" "next" "nor" "not" "null" "of" "on" "open" "or" "others" "out" "package" "port" "postponed" "procedure" "process" "pure" "range" "record" "register" "reject" "rem" "report" "return" "rol" "ror" "select" "severity" "signal" "shared" "sla" "sll" "sra" "srl" "subtype" "then" "to" "transport" "type" "unaffected" "units" "until" "use" "variable" "wait" "when" "while" "with" "xnor" "xor"} -case_insensitive -replacement_char "x" -special sge_vhdl#@ define_name_rules sge_vhdl -type net -allowed "A-Z a-z _ 0-9 ()" -first_restricted "0-9 _()" -last_restricted "_"#@ define_name_rules sge_vhdl -type port -allowed "A-Z a-z _ 0-9 ()" -first_restricted "0-9 _()" -last_restricted "_"#@ define_name_rules sge_vhdl -type cell -allowed "A-Z a-z _ 0-9" -first_restricted "0-9 _" -last_restricted "_"#@#@ ####/* Name rule for VHDL */#@#@ define_name_rules vhdl -reserved_words { "abs" "access" "after" "alias" "all" "and" "architecture" "array" "assert" "attribute" \#@ "begin" "block" "body" "buffer" "bus" "case" "component" "configuration" "constant" "disconnect" "downto" "else" "elsif" "end" "entity" "exit" "file" "for" "function" "generate" "generic" "group" "guarded" "if" "impure" "in" "inertial" "inout" "is" "label" "library" "linkage" "literal" "loop" "map" "mod" "nand" "new" "next" "nor" "not" "null" "of" "on" "open" "or" "others" "out" "package" "port" "postponed" "procedure" "process" "pure" "range" "record" "register" "reject" "rem" "report" "return" "rol" "ror" "select" "severity" "signal" "shared" "sla" "sll" "sra" "srl" "subtype" "then" "to" "transport" "type" "unaffected" "units" "until" "use" "variable" "wait" "when" "while" "with" "xnor" "xor"} -case_insensitive -target_bus_naming_style "%s(%d)" -replacement_char "x" -special vhdl#@ define_name_rules vhdl -type net -allowed "A-Z a-z _ 0-9 ()" -first_restricted "0-9 _()" -last_restricted "_"#@ define_name_rules vhdl -type port -allowed "A-Z a-z _ 0-9 ()" -first_restricted "0-9 _()" -last_restricted "_"#@ define_name_rules vhdl -type cell -allowed "A-Z a-z _ 0-9" -first_restricted "0-9 _" -last_restricted "_"#@ ####/* Name rule for VHDL */#@#@ define_name_rules vhdl93 -reserved_words { "abs" "access" "after" "alias" "all" "and" "architecture" "array" "assert" "attribute" "begin" "block" "body" "buffer" "bus" "case" "component" "configuration" "constant" "disconnect" "downto" "else" "elsif" "end" "entity" "exit" "file" "for" "function" "generate" "generic" "group" "guarded" "if" "impure" "in" "inertial" "inout" "is" "label" "library" "linkage" "literal" "loop" "map" "mod" "nand" "new" "next" "nor" "not" "null" "of" "on" "open" "or" "others" "out" "package" "port" "postponed" "procedure" "process" "pure" "range" "record" "register" "reject" "rem" "report" "return" "rol" "ror" "select" "severity" "signal" "shared" "sla" "sll" "sra" "srl" "subtype" "then" "to" "transport" "type" "unaffected" "units" "until" "use" "variable" "wait" "when" "while" "with" "xnor" "xor"} -case_insensitive -target_bus_naming_style "%s(%d)" -replacement_char "x" -special vhdl93#@ define_name_rules vhdl93 -type net -allowed "\\\\ A-Z a-z _ 0-9 ()" -first_restricted "0-9 _()" -last_restricted "_"#@ define_name_rules vhdl93 -type port -allowed "\\\\ A-Z a-z _ 0-9 ()" -first_restricted "0-9 _()" -last_restricted "_"#@ define_name_rules vhdl93 -type cell -allowed "\\\\ A-Z a-z _ 0-9" -first_restricted "0-9 _" -last_restricted "_"#@#@#@ ###/* Name rule for VHDL */#@#@ define_name_rules vhdl_ds -reserved_words { "abs" "access" "after" "alias" "all" "and" "architecture" "array" "assert" "attribute" "begin" "block" "body" "buffer" "bus" "case" "component" "configuration" "constant" "disconnect" "downto" "else" "elsif" "end" "entity" "exit" "file" "for" "function" "generate" "generic" "group" "guarded" "if" "impure" "in" "inertial" "inout" "is" "label" "library" "linkage" "literal" "loop" "map" "mod" "nand" "new" "next" "nor" "not" "null" "of" "on" "open" "or" "others" "out" "package" "port" "postponed" "procedure" "process" "pure" "range" "record" "register" "reject" "rem" "report" "return" "rol" "ror" "select" "severity" "signal" "shared" "sla" "sll" "sra" "srl" "subtype" "then" "to" "transport" "type" "unaffected" "units" "until" "use" "variable" "wait" "when" "while" "with" "xnor" "xor"} -case_insensitive -inout_ports_equal_nets -replacement_char "x" -special vhdl#@ define_name_rules vhdl_ds -type net -allowed "A-Z a-z _ 0-9 ()" -first_restricted "0-9 _()" -last_restricted "_"#@ define_name_rules vhdl_ds -type port -allowed "A-Z a-z _ 0-9 ()" -first_restricted "0-9 _()" -last_restricted "_"#@ define_name_rules vhdl_ds -type cell -allowed "A-Z a-z _ 0-9" -first_restricted "0-9 _" -last_restricted "_"#@#@ #/****#@ # Verilog rules: Verilog allows alphanumerics and underscore in#@ # names. The first character must be alphabetic. Nets, ports,#@ # and cells share the same name space; they cannot have the same#@ # name. A slew of reserved words are defined.#@ #****/#@ define_name_rules verilog -type net -allow {a-z A-Z 0-9 _ \[\]} -first_restrict "_ 0-9"#@#@ define_name_rules verilog -type port -allow {a-z A-Z 0-9 _ \[\]} -first_restrict "_ 0-9"#@#@ define_name_rules verilog -type cell -allow "a-z A-Z 0-9 _ " -first_restrict "_ 0-9"#@#@ define_name_rules verilog -reserved { "always" "and" "assign" "begin" "buf" "bufif0" "bufif1" "case" "casex" "casez" "cmos" "deassign" "default" "defparam" "disable" "edge" "else" "end" "endattribute" "endcase" "endfunction" "endmodule" "endprimitive" "endspecify" "endtable" "endtask" "event" "for" "force" "forever" "fork" "function" "highz0" "highz1" "if" "initial" "inout" "input" "integer" "join" "large" "macromodule" "medium" "module" "nand" "negedge" "nmos" "nor" "not" "notif0" "notif1" "or" "output" "parameter" "pmos" "posedge" "primitive" "pull0" "pull1" "pullup" "pulldown" "reg" "rcmos" "reg" "release" "repeat" "rnmos" "rpmos" "rtran" "rtranif0" "rtranif1" "scalared" "small" "specify" "specparam" "strength" "strong0" "strong1" "supply0" "supply1" "table" "task" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1" "trinand" "trior" "trireg" "use" "vectored" "wait" "wand" "weak0" "weak1" "while" "wire" "wor" "xor" "xnor" } -special verilog -target_bus_naming_style{%s[%d]}#@ # -- End source /usr/synopsys/synthesis/admin/setup/.dc_name_rules#@#@#@ #/* Read budgeting setup script */#@#@ if { [string compare $dc_shell_mode "default"] == 0 } {#@#@ # Need a encrypted file in Tcl format for budget.setup.et#@ if { $sh_arch != "msvc50" && $sh_arch != "alpha_nt" } {#@ # source -e synopsys_root + "/admin/setup/budget.setup.et"#@ }#@ }#@#@ # alias for write_sge is always the last line of the setup file#@ if { [string compare $dc_shell_mode "tcl"] == 0 } {#@ alias write_sge "source db2sge_script"#@ } else {#@ alias write_sge "include db2sge_script"#@ }#@#@ # True if executing Design Vision or PC-Gui#@ if { $synopsys_program_name == "design_vision" || $synopsys_program_name == "psyn_gui" } {#@#@ # Configure online help and user guide documentation#@ set dv_tutorial "doc/online/synth/dvtut/toc.pdf"#@ set dv_userguide "doc/online/synth/dvug/toc.pdf"#@ set dv_online_help "doc/online/synth/dvoh/dv_help.html"#@#@ # Turn this on to speed up the schematic generation, other wise it may take hours#@ set sort_outputs "true"#@#@ # Configure schematic setup#@ source $synopsys_root/admin/setup/.dv_schematic_setup#@#@ # True if in TCL mode#@ if { $dc_shell_mode == "tcl" } {#@#@ # Sources Design Vision specific procedures#@ source $synopsys_root/auxx/syn/.dv_procs.tcl#@#@ # Configure Execute script dialog to display .tcl files#@ set view_execute_script_suffix "$view_execute_script_suffix .tcl"#@#@ # Configure "Tools -> User Scripts" menu#@ set view_script_submenu_items { "Report Selected" "report_selected" "Select Path Hierarchy" "select_path_hier"}#@#@ if { ![string compare $synopsys_program_name "psyn_gui"] } {#@ if { [file exists [file join $synopsys_root auxx syn .psyn_gui_setup.tcl]] } {#@ source [file join $synopsys_root auxx syn .psyn_gui_setup.tcl]#@ } else {#@ echo "Warning: could not find file .psyn_gui_setup.tcl in installation"#@ }#@ }#@ }#@ }#@#@ # -- End source /usr/synopsys/synthesis/admin/setup/.synopsys_dc.setupsource -echo -verbose /home/fabrizio/m1_core/hdl/filelist.dc#@ # Synthesis script for dc_shell (Tcl mode)#@#@ # Analyze#@ set search_path [concat [list /home/fabrizio/m1_core/hdl/rtl/m1_cpu] $search_path]#@ analyze -format verilog ~/m1_core/hdl/rtl/m1_cpu/m1_alu.v#@ analyze -format verilog ~/m1_core/hdl/rtl/m1_cpu/m1_cpu.v#@#@ # Elaborate#@ elaborate m1_cpu#@ link#@ uniquify#@ check_design#@#@ # Constraints#@ create_clock -name "sys_clock_i" -period 2.0 -waveform {0 1.0} [get_ports "sys_clock_i"]#@ set_dont_touch_network [get_clocks "sys_clock_i"]#@ set_input_delay 1.25 -max -rise -clock "sys_clock_i" [get_ports "sys_reset_i"]#@ set_input_delay 1.25 -max -fall -clock "sys_clock_i" [get_ports "sys_reset_i"]#@ set_output_delay 1.25 -clock sys_clock_i -max -rise [all_outputs]#@ set_output_delay 1.25 -clock sys_clock_i -max -fall [all_outputs]#@ set_wire_load_mode "enclosed"#@#@ # Compile#@ compile
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