Subversion Repositories m1_core

M1 Core ("Mistral") TODO List
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Implementation
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At the moment the CPU has no exception nor external interrupt handling.


Functional Verification
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Several simulations have been performed by Fabio Motta, Simone Lunardo and Paolo Piscopo.


Open issues
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- Jump are working (J JAL JR JALR) including the delay slot;
- equality branches (BEQ BNE) executed 2 delay slots rather than just 1, should be correct now;
- disequality branches (BLEZ BGTZ BLTZ BGEZ) do not work yet.