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Simply RISC M1 Core ("Mistral") TODO List
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Implementation
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Current implementation lacks separate L1 caches (there's a unified L2 into the DDR Controller).
Also an INTC (Interrupt Controller) should be required to handle 32 IRQs and pass only one to the CPU.
The CPU has no interrupt handling at all so it must be added.


ISA Functional Verification
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Several simulations have been performed by Simone Lunardo and Paolo Piscopo;
the verification status for each instruction is as follows:

- LOAD/STORE
Only 32-bit LW/SW have been tested and they work.
Other sizes are not working.
Unaligned accesses are not implemented at all.

- ALU I-TYPE, ALU R-TYPE, SHIFT, MULTIPLY-DIVIDE
All tested and working.

- JUMP/BRANCH
Jump are working (J JAL JR JALR) including the delay slot.
Equality branches (BEQ BNE) execute 2 delay slots rather than just 1.
Disequality branches (BLEZ BGTZ BLTZ BGEZ) do not work.