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Simply RISC M1 Core ("Mistral") TODO List
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Implementation
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At the moment the CPU has no exception nor external interrupt handling.


Functional Verification
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Several simulations have been performed by Fabio Motta, Simone Lunardo and Paolo Piscopo.


Open issues
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While Jump are working (J JAL JR JALR) including the delay slot,
equality branches (BEQ BNE) execute 2 delay slots rather than just 1
and disequality branches (BLEZ BGTZ BLTZ BGEZ) do not work yet.