Subversion Repositories m1_core

# Synthesis script for dc_shell (Tcl mode)

# Analyze

analyze -format verilog ~/m1_core/trunk/hdl/rtl/m1_core/trunk/m1_alu.v
analyze -format verilog ~/m1_core/trunk/hdl/rtl/m1_core/trunk/m1_mul.v
analyze -format verilog ~/m1_core/trunk/hdl/rtl/m1_core/trunk/m1_div.v
analyze -format verilog ~/m1_core/trunk/hdl/rtl/m1_core/trunk/m1_cpu.v
analyze -format verilog ~/m1_core/trunk/hdl/rtl/m1_core/trunk/m1_mmu.v
analyze -format verilog ~/m1_core/trunk/hdl/rtl/m1_core/trunk/m1_core.v

# Technology-independent elaboration and linking

set active_design m1_core
elaborate $active_design
current_design $active_design
link
uniquify

# Constraints and mapping on target library

create_clock -period 4.0 -waveform [list 0 2.0] sys_clock_i
set_input_delay 2.0 -clock sys_clock_i -max [all_inputs]
set_output_delay 1.0 -clock sys_clock_i -max [all_outputs]
set_dont_touch_network [list sys_clock_i sys_reset_i]
set_drive 0 [list sys_clock_i sys_reset_i]
set_wire_load_mode enclosed
set_max_area 0
set_fix_multiple_port_nets -buffer_constants -all
compile

# Export the mapped design

remove_unconnected_ports [find -hierarchy cell {"*"}]
write -format ddc -hierarchy -output $active_design.ddc
write -format verilog -hierarchy -output $active_design.sv

# Report area and timing

report_area -hierarchy > report_area.rpt
report_timing > report_timing.rpt
report_constraint -all_violators > report_constraint.rpt

quit