URL
https://opencores.org/ocsvn/mac_layer_switch/mac_layer_switch/trunk
Subversion Repositories mac_layer_switch
[/] [mac_layer_switch/] [trunk/] [bench/] [verilog/] [ethmac.vpj] - Rev 2
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<!DOCTYPE Project SYSTEM "http://www.slickedit.com/dtd/vse/9.0/vpj.dtd">
<Project
Version="9.0"
VendorName="SlickEdit"
WorkingDir=".">
<Config
Name="Release"
OutputFile=""
CompilerConfigName="Latest Version">
<Includes>
<Include Dir="%(INCLUDE)"/>
</Includes>
<Menu>
<Target
Name="Compile"
MenuCaption="&Compile"
CaptureOutputWith="ProcessBuffer"
SaveOption="SaveCurrent"
RunFromDir="%rw">
<Exec CmdLine="vlog %p%n%e"/>
</Target>
<Target
Name="Build"
MenuCaption="&Build"
CaptureOutputWith="ProcessBuffer"
SaveOption="SaveWorkspaceFiles"
RunFromDir="%rw">
<Exec CmdLine="nmake"/>
</Target>
<Target
Name="Rebuild"
MenuCaption="&Rebuild"
CaptureOutputWith="ProcessBuffer"
SaveOption="SaveWorkspaceFiles"
RunFromDir="%rw">
<Exec CmdLine="nmake /A"/>
</Target>
<Target
Name="Debug"
MenuCaption="&Debug"
SaveOption="SaveNone"
RunFromDir="%rw">
<Exec CmdLine="vsim"/>
</Target>
<Target
Name="Execute"
MenuCaption="E&xecute"
SaveOption="SaveNone"
RunFromDir="%rw">
<Exec CmdLine="vsim"/>
</Target>
</Menu>
</Config>
<Files>
<Folder
Name="Source Files"
Filters="*.v;*.verilog">
<F N="../../rtl/verilog/eth_clockgen.v"/>
<F N="../../rtl/verilog/eth_cop.v"/>
<F N="../../rtl/verilog/eth_crc.v"/>
<F N="../../rtl/verilog/eth_fifo.v"/>
<F N="../../rtl/verilog/eth_l3_checksum .v"/>
<F N="../../rtl/verilog/eth_maccontrol.v"/>
<F N="../../rtl/verilog/eth_macstatus.v"/>
<F N="../../rtl/verilog/eth_miim.v"/>
<F N="../../rtl/verilog/eth_outputcontrol.v"/>
<F N="../../rtl/verilog/eth_random.v"/>
<F N="../../rtl/verilog/eth_receivecontrol.v"/>
<F N="../../rtl/verilog/eth_register.v"/>
<F N="../../rtl/verilog/eth_registers.v"/>
<F N="../../rtl/verilog/eth_rxaddrcheck.v"/>
<F N="../../rtl/verilog/eth_rxcounters.v"/>
<F N="../../rtl/verilog/eth_rxethmac.v"/>
<F N="../../rtl/verilog/eth_rxstatem.v"/>
<F N="../../rtl/verilog/eth_shiftreg.v"/>
<F N="../../rtl/verilog/eth_spram_256x32.v"/>
<F N="../../rtl/verilog/eth_top.v"/>
<F N="../../rtl/verilog/eth_transmitcontrol.v"/>
<F N="../../rtl/verilog/eth_txcounters.v"/>
<F N="../../rtl/verilog/eth_txethmac.v"/>
<F N="../../rtl/verilog/eth_txstatem.v"/>
<F N="../../rtl/verilog/eth_wishbone.v"/>
<F N="../../rtl/verilog/ethmac.v"/>
<F N="../../rtl/verilog/ethmac_defines.v"/>
<F N="../../rtl/verilog/plu_moduls.v"/>
<F N="../../rtl/verilog/switch.v"/>
<F N="../../rtl/verilog/timescale.v"/>
<F N="../../rtl/verilog/xilinx_dist_ram_16x32.v"/>
</Folder>
<Folder
Name="Other Files"
Filters="">
<F N="../../rtl/verilog/BUGS"/>
<F N="../../rtl/verilog/ethmac.vpj"/>
<F N="../../rtl/verilog/ethmac.vpw"/>
<F N="../../rtl/verilog/ethmac.vpwhist"/>
<F N="../../rtl/verilog/ethmac.vtg"/>
<F N="../../rtl/verilog/TODO"/>
</Folder>
</Files>
</Project>