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[/] [manchesterencoderdecoder/] [web_uploads/] [ME2.vhd] - Rev 6
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library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; entity me is port ( rst : in std_logic; -- Power On Reset Active High rts : in std_logic; -- Request To Send Active Low txd : in std_logic; -- Data To Be Transmitted clkin : in std_logic ; -- Clk Input cts : out std_logic ; -- Clear to Sen Output Active Low txcout : out std_logic; -- TX CLK = just clkin /16 txlen : out std_logic; -- TX Enable Active High mdo : out std_logic -- Manchester Encoded Data Output (TX "01" for 1 and "10" for 0) ) ; end me ; ------------------------------------------------------------------------------- architecture rtl of me is ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- begin -- architecture rtl ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- main : process (rst, clkin) ------------------------------------------------------------------------------- type state_t is ( idle, preamble, postpreamble, sending, eom ); variable state : state_t; variable PrCounter : integer range 0 to 31; variable TxCounter : integer range 0 to 15; -- variables to hold the internal value of the output ports: variable TXCOUT_i : std_logic; variable CTS_i : std_logic; variable MDO_i : std_logic; variable MDO_i1 : std_logic; variable TXLEN_i : std_logic; ------------------------------------------------------------------------------- begin ------------------------------------------------------------------------------- if rst='1' then ------------------------------------------------------------------------------- --asynchronously reset all internal variables state := idle; PrCounter := 30 ; -- adjunt to length of your preamble TxCounter := 0 ; TXCOUT_i := '0'; CTS_i := '1'; MDO_i := '0'; MDO_i1 := '0'; TXLEN_i := '0'; ------------------------------------------------------------------------------- elsif clkin'event and clkin='1' then ------------------------------------------------------------------------------- --counter for clkin/16 --must txcout have a 50% duty cycle? TxCounter := (TxCounter + 1) mod 16; if TxCounter = 0 then TXCOUT_i := '0'; end if; if TxCounter = 8 then TXCOUT_i := '1'; end if; ------------------------------------------------------------------------------- case state is ------------------------------------------------------------------------------- when idle => if rts = '0' then state := preamble; PrCounter := 30 ; MDO_i := '0'; end if; ------------------------------------------------------------------------------- when preamble => if TxCounter = 8 then --when to mark? 2? 3? ..7? 8? TXLEN_i := '1'; --when will it be turned off ? never? end if; if TxCounter = 8 then --when to toggle? 2? 3? .. 6? MDO_i := not(MDO_i); --preamble 15 times '10' PrCounter := PrCounter - 1; if PrCounter = 0 then state := postpreamble; PrCounter := 2; -- adjunt to length of your post-preamble. end if; end if; ------------------------------------------------------------------------------- when postpreamble => if TxCounter = 8 then --when to toggle? 2? 3? .. 6? MDO_i := '1'; -- post preamble: '11' PrCounter := PrCounter - 1; if PrCounter = 0 then --MDO_i := txd; state := sending; CTS_i := '0'; --when will it be turned off ? never? end if; end if; ------------------------------------------------------------------------------- when sending => if TxCounter = 8 then --this samples the date with clkin, not with txcout.. --what is actually needed ? MDO_i := txd; if (rts = '1') then state := eom; PrCounter := 2; CTS_i := '1'; MDO_i := '1'; end if; end if; when eom => if TxCounter = 8 then MDO_i := '1'; PrCounter := PrCounter - 1; if PrCounter = 0 then state := idle; end if; end if; --manchester encoding not yet implemented, too many open questions.. --to many unspecified specifications ;)! --how to return to idle? ------------------------------------------------------------------------------- when others => state := idle; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- end case; if state /= idle then if state = eom then MDO_i1 := MDO_i; elsif TxCounter = 8 then TXLEN_i := '1'; MDO_i1 := not MDO_i; elsif TxCounter = 0 then MDO_i1 := MDO_i; end if; elsif TXCounter = 8 then TXLEN_i := '0'; end if; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- end if; ------------------------------------------------------------------------------- --assign output ports: txcout <= TXCOUT_i; cts <= CTS_i; mdo <= MDO_i1; txlen <= TXLEN_i; ------------------------------------------------------------------------------- end process main; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- end ; -- architecture rtl ------------------------------------------ -- ME2.vhd