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[/] [mb-jpeg/] [tags/] [STEP1_1/] [microblaze_0/] [include/] [xparameters.h] - Rev 66
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/******************************************************************* * * CAUTION: This file is automatically generated by libgen. * Version: Xilinx EDK 7.1.2 EDK_H.12.5.1 * DO NOT EDIT. * * Copyright (c) 2005 Xilinx, Inc. All rights reserved. * * Description: Driver parameters * *******************************************************************/ #define STDIN_BASEADDRESS 0x40600000 #define STDOUT_BASEADDRESS 0x40600000 /******************************************************************/ #define XPAR_DLMB_CNTLR_BASEADDR 0x00000000 #define XPAR_DLMB_CNTLR_HIGHADDR 0x0000FFFF #define XPAR_DATA_BRAM_IF_CNTLR_0_BASEADDR 0x70000000 #define XPAR_DATA_BRAM_IF_CNTLR_0_HIGHADDR 0x7000FFFF #define XPAR_DATA_BRAM_IF_CNTLR_1_BASEADDR 0x70010000 #define XPAR_DATA_BRAM_IF_CNTLR_1_HIGHADDR 0x7001FFFF #define XPAR_ILMB_CNTLR_BASEADDR 0x00000000 #define XPAR_ILMB_CNTLR_HIGHADDR 0x0000FFFF /******************************************************************/ #define XPAR_XUARTLITE_NUM_INSTANCES 2 #define XPAR_DEBUG_MODULE_BASEADDR 0x41400000 #define XPAR_DEBUG_MODULE_HIGHADDR 0x4140FFFF #define XPAR_DEBUG_MODULE_DEVICE_ID 0 #define XPAR_DEBUG_MODULE_BAUDRATE 0 #define XPAR_DEBUG_MODULE_USE_PARITY 0 #define XPAR_DEBUG_MODULE_ODD_PARITY 0 #define XPAR_DEBUG_MODULE_DATA_BITS 0 #define XPAR_RS232_UART_1_BASEADDR 0x40600000 #define XPAR_RS232_UART_1_HIGHADDR 0x4060FFFF #define XPAR_RS232_UART_1_DEVICE_ID 1 #define XPAR_RS232_UART_1_BAUDRATE 9600 #define XPAR_RS232_UART_1_USE_PARITY 0 #define XPAR_RS232_UART_1_ODD_PARITY 0 #define XPAR_RS232_UART_1_DATA_BITS 8 /******************************************************************/ #define XPAR_XSYSACE_MEM_WIDTH 16 #define XPAR_XSYSACE_NUM_INSTANCES 1 #define XPAR_SYSACE_COMPACTFLASH_BASEADDR 0x41800000 #define XPAR_SYSACE_COMPACTFLASH_HIGHADDR 0x4180FFFF #define XPAR_SYSACE_COMPACTFLASH_DEVICE_ID 0 #define XPAR_SYSACE_COMPACTFLASH_MEM_WIDTH 16 /******************************************************************/ #define XPAR_XGPIO_NUM_INSTANCES 3 #define XPAR_LEDS_4BIT_BASEADDR 0x40020000 #define XPAR_LEDS_4BIT_HIGHADDR 0x4002FFFF #define XPAR_LEDS_4BIT_DEVICE_ID 0 #define XPAR_LEDS_4BIT_INTERRUPT_PRESENT 0 #define XPAR_LEDS_4BIT_IS_DUAL 0 #define XPAR_DIPSWS_4BIT_BASEADDR 0x40040000 #define XPAR_DIPSWS_4BIT_HIGHADDR 0x4004FFFF #define XPAR_DIPSWS_4BIT_DEVICE_ID 1 #define XPAR_DIPSWS_4BIT_INTERRUPT_PRESENT 0 #define XPAR_DIPSWS_4BIT_IS_DUAL 0 #define XPAR_PUSHBUTTONS_5BIT_BASEADDR 0x40000000 #define XPAR_PUSHBUTTONS_5BIT_HIGHADDR 0x4000FFFF #define XPAR_PUSHBUTTONS_5BIT_DEVICE_ID 2 #define XPAR_PUSHBUTTONS_5BIT_INTERRUPT_PRESENT 0 #define XPAR_PUSHBUTTONS_5BIT_IS_DUAL 0 /******************************************************************/ #define XPAR_CPU_CORE_CLOCK_FREQ_HZ 100000000 /******************************************************************/ #define XILFATFS_MAXFILES 5 #define XILFATFS_BUFCACHE_SIZE 10240