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-- Company:        Ferhat Abbas University - Algeria
-- Engineer:       Ibrahim MEZZAH
-- Progect Supervisor: Dr H. Chemali
-- Create Date:    01:15:35 07/17/05
-- Design Name:    8-bits arithmetic and logic unit (2)
-- Module Name:    ALU - simple
-- Project Name:   Microcontroller IP (MCIP)
-- Target Device:  xc3s500e-4fg320
-- Tool versions:  Xilinx ISE 9.1.03i
-- Description:	 This ALU is based on 8 simple slices. This module:
--						 operates on A, B and using Old status,
--						 provides the result S and the New status.
-- Revision: 		 07/07/2008
-- Revision  2.2 - Add description
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity ALU is
    Port ( CommandVector : in std_logic_vector(13 downto 0);
           CommandStatus : in std_logic_vector(4 downto 0);
			  OldStatus     : in std_logic_vector(4 downto 0);
			  a             : in std_logic_vector(7 downto 0);
           b             : in std_logic_vector(7 downto 0);
           s             : out std_logic_vector(7 downto 0);
           NewStatus     : out std_logic_vector(4 downto 0);
           SetResponse   : out std_logic_vector(1 downto 0));
end ALU;
 
architecture simple of ALU is
	component alu_slice
    Port ( g  : in  std_logic_vector(3 downto 0);
           p  : in  std_logic_vector(3 downto 0);
           a  : in  std_logic;
           b  : in  std_logic;
           ci : in  std_logic;
           s  : out std_logic;
           co : out std_logic);
	end component;
 
	signal ci : std_logic_vector(7 downto 0);
	signal co : std_logic_vector(7 downto 0);
	signal ai : std_logic_vector(7 downto 0);
	signal bi : std_logic_vector(7 downto 0);
	signal si : std_logic_vector(7 downto 0);
	signal CurrentStatus : std_logic_vector(4 downto 0);
	signal cr0 : std_logic;
	signal cr7 : std_logic;
	signal C   : std_logic;
	signal DC  : std_logic;
	signal Z   : std_logic;
	signal OV  : std_logic;
	signal N   : std_logic;
	signal test_bit : std_logic;
 
	signal SWAPa  : std_logic_vector(7 downto 0);
	signal S_D    : std_logic_vector(7 downto 0);
	signal BITOPa : std_logic_vector(7 downto 0);
	signal DAW_op : std_logic_vector(7 downto 0);
 
	alias v : std_logic_vector(13 downto 0) is CommandVector;
 
begin
 
slices: for i in 0 to 7 generate
	slice: alu_slice
		port map( g  => v(3 downto 0),
					 p  => v(7 downto 4),
					 a  => ai(i),
					 b  => bi(i),
					 ci => ci(i),
					 s  => si(i),
					 co => co(i)
				  );
	end generate;
 
	cr0 <= a(1)							when v(11) = '1' else
			 a(7);
	cr7 <= a(0)							when v(10) = '1' else
			 OldStatus(0);
 
	ci(0) <= '0'							when v(13 downto 12) = "00" else
				'1'							when v(13 downto 12) = "01" else
				cr0							when v(13 downto 12) = "10" else
				OldStatus(0);
	ci(7) <= cr7							when v(11) = '1' else
				co(6);
 
	C <= co(0)								when v(11) = '1' else
		  co(7);
	DC <= ci(4);
	Z <= '1'									when si = X"00" else
		  '0';
	N <= si(7);
	OV <= '1'
	when((v(0)='0' and v(1)='1' and N='1' and a(7)='0' and b(7)='0') or
		  (v(0)='0' and v(1)='1' and N='0' and a(7)='1' and b(7)='1') or
 
		  (v(0)='0' and v(1)='0' and N='1' and a(7)='0') or
 
		  (v(0)='1' and v(1)='0' and v(5)='0' and N='0' and a(7)='1' and b(7)='0') or
		  (v(0)='1' and v(1)='0' and v(5)='0' and N='1' and a(7)='0' and b(7)='1') or
 
		  (v(0)='1' and v(7)='1' and N='0' and a(7)='1') or
 
		  (v(0)='1' and v(1)='0' and v(5)='1' and N='1' and a(7)='1' and b(7)='0') or
		  (v(0)='1' and v(1)='0' and v(5)='1' and N='0' and a(7)='0' and b(7)='1') or
 
		  (v(0)='1' and v(1)='1' and v(7)='0' and N='1' and a(7)='1') ) else
			'0';																								
 
	CurrentStatus <= N&OV&Z&DC&C;
 
	SWAPa <= a(3 downto 0) & a(7 downto 4);
 
	DAW_op(3 downto 0) <= X"6"
	when ((b(3 downto 0) > "1001") or OldStatus(1)='1') else
								 X"0";
	DAW_op(7 downto 4) <= X"6"		when ((b(7 downto 4) > "1001") or OldStatus(0)='1'
													or (b(7 downto 4)="1001" and DC='1')) else
								 X"0";
 
	S_D <= DAW_op							when V(10) = '0' else
			 SWAPa;
 
	ai <= BITOPa							when v(8) = '0' else
			S_D								when v(9) = '0' else
			a;
	bi <= b;
 
	SetResponse(0) <= test_bit			when v(8) = '0' else
							N;
	SetResponse(1) <= Z;
 
Carry : process(v(13 downto 11), a, co, cr0, cr7, OldStatus(0))
	begin
		for i in 0 to 7 loop
		  if i = 0 then
			if v(13 downto 12) = "00" then
			  ci(i) <= '0';
			elsif v(13 downto 12) = "01" then
			  ci(i) <= '1';
			elsif v(13 downto 12) = "10" then
			  ci(i) <= cr0;
			else
			  ci(i) <= OldStatus(0);
			end if;
		  elsif i = 7 then
			if v(11) = '1' then
			  ci(i) <= cr7;
			else
			  ci(i) <= co(6);
			end if;
		  else
			if v(11) = '1' then
			  ci(i) <= a(i+1);
			else
			  ci(i) <= co(i-1);
			end if;
		  end if;
		end loop;
	end process;
 
Bit_op : process(a, b(2 downto 0), v(10 downto 9))
	begin
		for i in 0 to 7 loop
		if i = conv_integer(b(2 downto 0)) then
		  if v(9) = '1' then
			 BITOPa(i) <= not a(i);
		  elsif v(10) = '0' then
			 BITOPa(i) <= '0';
		  else
			 BITOPa(i) <= '1';
		  end if;
		  test_bit <= a(i);
		else
		  BITOPa(i) <= a(i);
		end if;
		end loop;
	end process;
 
Status : process(OldStatus, CommandStatus, CurrentStatus)
	begin
		for i in 0 to 4 loop
		if CommandStatus(i) = '1' then
		  NewStatus(i) <= CurrentStatus(i);
		else
		  NewStatus(i) <= OldStatus(i);
		end if;
		end loop;
	end process;
 
	s <= si;
 
end simple;