Subversion Repositories mcip_open

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-- Company:        Ferhat Abbas University - Algeria
-- Engineer:       Ibrahim MEZZAH
-- Progect Supervisor: Dr H. Chemali
-- Create Date:    20:38:55 05/21/01
-- Design Name:    Data adress provider
-- Module Name:    Control_Address - Address
-- Project Name:   Microcontroller IP (MCIP)
-- Target Device:  xc3s500e-4fg320
-- Tool versions:  Xilinx ISE 9.1.03i
-- Description:	 This module provides the adress of Data in Data Memory
--						 as specified in the instruction.
-- Revision: 		 07/06/2008
-- Revision  5
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity Address_Provider is
    Port ( Q1           : in std_logic;
			  Q4           : in std_logic;
           nreset       : in std_logic;
           IR11_0       : in std_logic_vector(11 downto 0);
           R_W          : in std_logic_vector(1 downto 0);
			  call_return  : in std_logic_vector(1 downto 0);
			  MovFF_enable : in std_logic;
			  load_BSR     : in std_logic;
           DATA         : inout std_logic_vector(7 downto 0);
           Address_RAM  : out std_logic_vector(11 downto 0));
end Address_Provider;
 
architecture Behavioral of Address_Provider is
 
	 signal BSR : std_logic_vector(3 downto 0);
 
	 signal Address : std_logic_vector(11 downto 0);
	 signal Address11_8 : std_logic_vector(3 downto 0);
 
	 signal data_read : std_logic_vector(7 downto 0);
 
	 signal BSRs : std_logic_vector(3 downto 0);
 
	 signal AB : std_logic_vector(3 downto 0);		-- Access Bank
 
	 signal Address_Latch : std_logic_vector(3 downto 0);
 
	 alias RE : std_logic is R_W(1);
	 alias WE : std_logic is R_W(0);
 
begin
 
	 Address11_8 <= IR11_0(11 downto 8)			 when MovFF_enable = '1' else
						 AB								 when IR11_0(8) = '0' else
						 BSR;
	 Address <= Address11_8 & IR11_0(7 downto 0);
 
	 Address_Latch <= IR11_0(4 downto 3) & IR11_0(1 downto 0);
 
	 data_read <= x"0"&BSR;
 
		 AB <= "0000"					  when ( IR11_0(7 downto 0) < x"80" ) else
			 	 "1111";
 
	 Address_RAM <= Address;
 
	 DATA <= data_read				  when (Q1 = '1' and RE = '1') else
			  (others => 'Z');
 
latchs :  process (nreset, Q4, WE, Address_Latch,
						IR11_0, load_BSR,
						call_return, BSRs, BSR)
  begin
	 if nreset = '0' then
		 BSR   <= (others => '0');
		 BSRs  <= (others => '0');
 
	 elsif (Q4'event and Q4='1') then 			
		  if WE = '1' then
			 case Address_Latch is
			  when "0000" =>  BSR  <= DATA(3 downto 0);
			  when others => null;
			 end case;
			else
				if load_BSR = '1' then
					BSR <= IR11_0(3 downto 0);	
				else
				  if call_return(1) = '1' then
				  if call_return(0) = '0' then
					BSRs <= BSR;						-- call
				  else
					BSR <= BSRs;						-- return
				  end if;
				  end if;
				end if;
		  end if;
	 end if;
  end process;
 
end Behavioral;