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[/] [mcip_open/] [trunk/] [MCIPopen_XilinxISEproject/] [CPU.vhd] - Rev 4
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-------------------------------------------------------------------------------- -- Company: Ferhat Abbas University - Algeria -- Engineer: Ibrahim MEZZAH -- Progect Supervisor: Dr H. Chemali -- Create Date: 18:40:51 06/05/05 -- Design Name: CPU assembly -- Module Name: CPU - CPUnit -- Project Name: Microcontroller IP (MCIP) -- Target Device: xc3s500e-4fg320 -- Tool versions: Xilinx ISE 9.1.03i -- Description: CPU compenents mapping (Instruction Decoder, Operation unit, -- Program counter, Address provider). -- Revision: 07/07/2008 -- Revision 2.2 - Add description -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity CPU is Generic ( STKPTR_length : integer := 5; -- Stack Pointer Length -- < 6 STVREN : std_logic := '1'); -- Stack Overflow/Underflow Reset Enable bit Port ( nreset : in std_logic; Q : in std_logic_vector(1 to 4); Instruction : in std_logic_vector(15 downto 0); DATA : inout std_logic_vector(7 downto 0); Istruction_address : out std_logic_vector(20 downto 0); Data_address : out std_logic_vector(11 downto 0); address_latch_port : out std_logic_vector(3 downto 0); r_w_ram : out std_logic_vector(1 downto 0); r_w_port : out std_logic_vector(1 downto 0); r_w_wdt : out std_logic_vector(1 downto 0); soft_reset_enable : out std_logic; sleep_mode_enable : out std_logic; clear_watchdog : out std_logic; stack_overflow : out std_logic ); end CPU; architecture CPUnit of CPU is component Instruction_Decoder Port ( nreset : in std_logic; Q1 : in std_logic; Q4 : in std_logic; Fetched_instruction : in std_logic_vector(15 downto 0); Data_add : in std_logic_vector(11 downto 0); New_status : in std_logic_vector(4 downto 0); Set_response : in std_logic_vector(1 downto 0); Data : inout std_logic_vector(7 downto 0); Command_vector_opu : out std_logic_vector(13 downto 0); Command_vector_pc : out std_logic_vector(6 downto 0); Command_status : out std_logic_vector(4 downto 0); Current_status : out std_logic_vector(4 downto 0); Bit_op : out std_logic_vector(2 downto 0); call_return : out std_logic_vector(1 downto 0); IR11_0 : out std_logic_vector(11 downto 0); r_w_ram : out std_logic_vector(1 downto 0); r_w_add_pr : out std_logic_vector(1 downto 0); r_w_opu : out std_logic_vector(1 downto 0); r_w_port : out std_logic_vector(1 downto 0); r_w_wdt : out std_logic_vector(1 downto 0); bit_op_enable : out std_logic; load_FREG : out std_logic; read_result : out std_logic; WREG_write_enable : out std_logic; MUL_enable : out std_logic; MOVFF_enable : out std_logic; load_BSR : out std_logic; soft_reset_enable : out std_logic; sleep_mode_enable : out std_logic; clear_watchdog : out std_logic ); end component Instruction_Decoder; component Operation_Unit Port ( nreset : in std_logic; Q : in std_logic_vector(1 to 4); CommandVector : in std_logic_vector(13 downto 0); CommandStatus : in std_logic_vector(4 downto 0); OldStatus : in std_logic_vector(4 downto 0); R_W : in std_logic_vector(1 downto 0); BitOp : in std_logic_vector(2 downto 0); call_return : in std_logic_vector(1 downto 0); Address_Latch : in std_logic_vector(1 downto 0); BitOp_enable : in std_logic; WREG_write : in std_logic; MUL_enable : in std_logic; Read_result : in std_logic; Load_FREG : in std_logic; DATA : inout std_logic_vector(7 downto 0); NewStatus : out std_logic_vector(4 downto 0); SetResponse : out std_logic_vector(1 downto 0) ); end component Operation_Unit; component Program_Counter Generic ( STKPTR_length : integer := 5; -- Stack Pointer Length -- < 6 STVREN : std_logic := '1'); -- Stack Overflow/Underflow Reset Enable bit Port ( nreset : in std_logic; Q2 : in std_logic; Q4 : in std_logic; Command_vector : in std_logic_vector(6 downto 0); Branch_data : in std_logic_vector(11 downto 0); stack_overflow : out std_logic; IAddress : out std_logic_vector(20 downto 1)); end component Program_Counter; component Address_Provider Port ( Q1 : in std_logic; Q4 : in std_logic; nreset : in std_logic; IR11_0 : in std_logic_vector(11 downto 0); R_W : in std_logic_vector(1 downto 0); call_return : in std_logic_vector(1 downto 0); MovFF_enable : in std_logic; load_BSR : in std_logic; DATA : inout std_logic_vector(7 downto 0); Address_RAM : out std_logic_vector(11 downto 0)); end component Address_Provider; --component Table_Read -- Port ( nreset : in std_logic; -- Q1 : in std_logic; -- Q4 : in std_logic; -- enable : in std_logic; -- r_w : in std_logic_vector(1 downto 0); -- IR1_0 : in std_logic_vector(1 downto 0); -- pm_data : in std_logic_vector(7 downto 0); -- PCIstruction_address : in std_logic_vector(IALength-1 downto 0); -- Data : inout std_logic_vector(7 downto 0); -- Istruction_address : out std_logic_vector(IALength-1 downto 0)); --end component Table_Read; signal Command_vector_opu : std_logic_vector(13 downto 0); signal Command_vector_pc : std_logic_vector(6 downto 0); signal Command_status : std_logic_vector(4 downto 0); signal PCIstruction_address : std_logic_vector(20 downto 1); signal Current_status : std_logic_vector(4 downto 0); signal New_status : std_logic_vector(4 downto 0); signal IR11_0 : std_logic_vector(11 downto 0); signal Data_address_s : std_logic_vector(11 downto 0); signal address_latch_cu : std_logic_vector(1 downto 0); signal Set_response : std_logic_vector(1 downto 0); signal Bit_op : std_logic_vector(2 downto 0); signal call_return : std_logic_vector(1 downto 0); signal r_w_add_pr : std_logic_vector(1 downto 0); signal r_w_opu : std_logic_vector(1 downto 0); signal bit_op_enable : std_logic; signal load_FREG : std_logic; signal read_result : std_logic; signal WREG_write_enable : std_logic; signal MUL_enable : std_logic; signal MOVFF_enable : std_logic; signal load_BSR : std_logic; begin InstructionDecoder : Instruction_Decoder Port map ( nreset => nreset, Q1 => Q(1), Q4 => Q(4), Fetched_instruction => Instruction, Data_add => Data_address_s, New_status => New_status, Set_response => Set_response, Data => Data, Command_vector_opu => Command_vector_opu, Command_vector_pc => Command_vector_pc, Command_status => Command_status, Current_status => Current_status, Bit_op => Bit_op, call_return => call_return, IR11_0 => IR11_0, r_w_ram => r_w_ram, r_w_add_pr => r_w_add_pr, r_w_opu => r_w_opu, r_w_port => r_w_port, r_w_wdt => r_w_wdt, bit_op_enable => bit_op_enable, load_FREG => load_FREG, read_result => read_result, WREG_write_enable => WREG_write_enable, MUL_enable => MUL_enable, MOVFF_enable => MOVFF_enable, load_BSR => load_BSR, soft_reset_enable => soft_reset_enable, sleep_mode_enable => sleep_mode_enable, clear_watchdog => clear_watchdog ); OperationUnit : Operation_Unit Port map ( nreset => nreset, Q => Q, CommandVector => Command_vector_opu, CommandStatus => Command_status, OldStatus => Current_status, R_W => r_w_opu, BitOp => Bit_op, call_return => call_return, Address_Latch => address_latch_cu, BitOp_enable => bit_op_enable, WREG_write => WREG_write_enable, MUL_enable => MUL_enable, Read_result => read_result, Load_FREG => load_FREG, DATA => DATA, -- Wregister => Wregister, NewStatus => New_status, SetResponse => Set_response ); PC : Program_Counter Generic map( STKPTR_length => STKPTR_length, STVREN => STVREN) Port map ( nreset => nreset, -- Q1 => Q(1), Q2 => Q(2), Q4 => Q(4), -- freeze => freeze, Command_vector => Command_vector_pc, Branch_data => IR11_0, -- R_W => r_w_pc, -- Data => DATA, stack_overflow => stack_overflow, IAddress => PCIstruction_address ); Address_RAM : Address_Provider Port map ( Q1 => Q(1), Q4 => Q(4), nreset => nreset, IR11_0 => IR11_0, -- Wregister => Wregister, R_W => r_w_add_pr, -- loadFSRx => load_FSRx, call_return => call_return, MovFF_enable => MOVFF_enable, load_BSR => load_BSR, -- INDFx_enable => INDFx_enable, DATA => DATA, -- SFR_ind => SFR_ind, Address_RAM => Data_address_s ); --Tab_read : Table_Read --Port map ( nreset => nreset, -- Q1 => Q(1), -- Q4 => Q(4), -- enable => tableread, -- r_w => r_w_tbr, -- IR1_0 => IR11_0(1 downto 0), -- pm_data => Instruction(7 downto 0), -- PCIstruction_address => PCIstruction_address, -- Data => DATA, -- Istruction_address => Istruction_address ); Istruction_address <= PCIstruction_address & '0'; address_latch_port <= IR11_0(4 downto 3)&IR11_0(1 downto 0); -- address_latch_tmr <= IR11_0(1 downto 0); address_latch_cu <= IR11_0(2)&IR11_0(0); Data_address <= Data_address_s; end CPUnit;