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[/] [mcip_open/] [trunk/] [MCIPopen_XilinxISEproject/] [Data_Memory_Banks_Controller.vhd] - Rev 4
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---------------------------------------------------------------------------------- -- Company: Ferhat Abbas University - Algeria -- Engineer: Ibrahim MEZZAH -- -- Create Date: 10:09:19 04/17/2012 -- Design Name: -- Module Name: Data_Memory_Controller - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Data_Memory_Banks_Controller is Generic (Banks_number : integer := 3; -- number of banks, min = 2, max = 16 dm_TOPaddr : std_logic_vector(11 downto 0) := x"07F"); Port ( RE : in std_logic; WE : in std_logic; Data_address : in std_logic_vector(11 downto 0); RE_bank : out std_logic; WE_bank : out std_logic; Bank_selection : out std_logic_vector(0 to Banks_number-1); Bank_data_address : out std_logic_vector(7 downto 0) ); end Data_Memory_Banks_Controller; architecture Behavioral of Data_Memory_Banks_Controller is signal over_address : std_logic; begin over_address <= '1' when Data_Address > dm_TOPaddr else '0'; RE_bank <= RE when over_address = '0' else '0'; WE_bank <= WE when over_address = '0' else '0'; Bank_data_address <= Data_address(7 downto 0); Bank_selection_p : process(Data_address(11 downto 8)) begin for i in 0 to Banks_number-1 loop if i = CONV_INTEGER(Data_address(11 downto 8)) then Bank_selection(i) <= '1'; else Bank_selection(i) <= '0'; end if; end loop; end process; end Behavioral;