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-------------------------------------------------------------------------------- -- Company: Ferhat Abbas University - Algeria -- Engineer: Ibrahim MEZZAH -- Progect Supervisor: Dr H. Chemali -- Create Date: 01:16:40 05/16/05 -- Design Name: Decoder -- Module Name: Decoder - Decode -- Project Name: Microcontroller IP (MCIP) -- Target Device: xc3s500e-4fg320 -- Tool versions: Xilinx ISE 9.1.03i -- Description: This module generate system commands -- by decoding instruction. -- Revision: 07/07/2008 -- Revision 3.2 - Add description -- Additional Comments: Decoder is based on instructions classification -- to optimize the code. -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Decoder is Port ( Instruction : in std_logic_vector(15 downto 0); Status : in std_logic_vector(4 downto 1); second_inst_ide : in std_logic_vector(2 downto 0); Command_vector_pc : out std_logic_vector(6 downto 0); Command_vector_opu : out std_logic_vector(13 downto 0); Command_status : out std_logic_vector(4 downto 0); second_inst_inf : out std_logic_vector(2 downto 0); Skip_inf : out std_logic_vector(4 downto 0); read_write : out std_logic_vector(1 downto 0); call_return : out std_logic_vector(1 downto 0); bit_op_enable : out std_logic; load_FREG : out std_logic; read_result : out std_logic; WREG_write_enable : out std_logic; MUL_enable : out std_logic; MOVFF_enable : out std_logic; load_BSR : out std_logic; nop_enable : out std_logic; -- retfie : out std_logic; soft_reset_enable : out std_logic; sleep_mode_enable : out std_logic; clear_watchdog : out std_logic; -- table_read : out std_logic; -- INDFx : out std_logic; literal_enable : out std_logic ); end Decoder; architecture Decode of Decoder is constant enable : std_logic := '1'; constant disable : std_logic := '0'; constant Enabled : std_logic := '1'; constant Disabled : std_logic := '0'; subtype Command_vector_opu_type is std_logic_vector(13 downto 0); subtype Command_status_type is std_logic_vector(4 downto 0); subtype Command_vector_pc_type is std_logic_vector(6 downto 0); -- Command vector for calcul unit ---------------------------- constant NOP : Command_vector_opu_type := "00011100000110"; constant ADDWF : Command_vector_opu_type := "00011110000110"; constant ADDWFC : Command_vector_opu_type := "11011110000110"; constant ANDWF : Command_vector_opu_type := "00011100001000"; constant CLRF : Command_vector_opu_type := "00011100000000"; constant COMF : Command_vector_opu_type := "00011100000011"; constant CPF : Command_vector_opu_type := "01011101001001"; constant DECF : Command_vector_opu_type := "00011111000011"; constant INCF : Command_vector_opu_type := "01011100001100"; constant IORWF : Command_vector_opu_type := "00011100001110"; constant MOVF : Command_vector_opu_type := "00011100001100"; constant MOVWF : Command_vector_opu_type := "00011100001010"; constant NEGF : Command_vector_opu_type := "01011100000011"; constant RLCF : Command_vector_opu_type := "11011111000000"; constant RLNCF : Command_vector_opu_type := "10011111000000"; constant RRCF : Command_vector_opu_type := "10101111000000"; constant RRNCF : Command_vector_opu_type := "10111111000000"; constant SETF : Command_vector_opu_type := "00011100001111"; constant SUBFWB : Command_vector_opu_type := "11011100101001"; constant SUBWF : Command_vector_opu_type := "01011101001001"; constant SUBWFB : Command_vector_opu_type := "11011101001001"; constant SWAPF : Command_vector_opu_type := "00010100001100"; constant TSTF : Command_vector_opu_type := "00011100001100"; constant XORWF : Command_vector_opu_type := "00011100000110"; constant BCF : Command_vector_opu_type := "00000000001100"; constant BSF : Command_vector_opu_type := "00010000001100"; constant BTF : Command_vector_opu_type := "00011000001100"; constant BTG : Command_vector_opu_type := "00011000001100"; constant DAW : Command_vector_opu_type := "00000110000110"; -------------------------------------------------------------- -- Command vector for status --------------------------------- constant allv : command_status_type := "11111"; constant ZN : command_status_type := "10100"; constant CZN : command_status_type := "10101"; constant C : command_status_type := "00001"; constant Z : command_status_type := "00100"; constant none : command_status_type := "00000"; -------------------------------------------------------------- -- Command vector for program counter ------------------------ constant increment : Command_vector_pc_type := "0001010"; constant branch_con : Command_vector_pc_type := "0001100"; constant branch_inc : Command_vector_pc_type := "0001110"; constant CALL1 : Command_vector_pc_type := "1001010"; constant CALL2 : Command_vector_pc_type := "1111010"; constant GOTO1 : Command_vector_pc_type := "1001010"; constant GOTO2 : Command_vector_pc_type := "1101010"; constant RCALL : Command_vector_pc_type := "0011110"; constant POP : Command_vector_pc_type := "0010010"; constant PUSH : Command_vector_pc_type := "0011010"; constant retur_n : Command_vector_pc_type := "0010011"; -------------------------------------------------------------- -- second instruction information ---------------------------- constant sec_disable : std_logic_vector(2 downto 0) := "011"; constant sec_MOVFF : std_logic_vector(2 downto 0) := "100"; -- constant sec_LFSRx : std_logic_vector(2 downto 0) := "101"; constant sec_GOTO : std_logic_vector(2 downto 0) := "110"; constant sec_CALL : std_logic_vector(2 downto 0) := "111"; -------------------------------------------------------------- -- Skip information ------------------------------------------ constant not_skip : std_logic_vector(4 downto 0) := "00011"; constant CPFSEQ : std_logic_vector(4 downto 0) := "11010"; constant CPFSGT : std_logic_vector(4 downto 0) := "10011"; constant CPFSLT : std_logic_vector(4 downto 0) := "10111"; constant SZ : std_logic_vector(4 downto 0) := "11010"; constant SNZ : std_logic_vector(4 downto 0) := "10010"; constant BTFSC : std_logic_vector(4 downto 0) := "10001"; constant BTFSS : std_logic_vector(4 downto 0) := "10101"; -------------------------------------------------------------- -- call-return ----------------------------------------------- constant none_action : std_logic_vector(1 downto 0) := "01"; constant call_action : std_logic_vector(1 downto 0) := "10"; constant return_action : std_logic_vector(1 downto 0) := "11"; -------------------------------------------------------------- -- load FSRx ------------------------------------------------- -- constant load_disable : std_logic_vector(1 downto 0) := "01"; -- constant enable_1stcyc : std_logic_vector(1 downto 0) := "10"; -- constant enable_2ndcyc : std_logic_vector(1 downto 0) := "11"; -------------------------------------------------------------- alias read_D : std_logic is read_write(1); alias write_D : std_logic is read_write(0); alias d : std_logic is Instruction(9); alias s1 : std_logic is Instruction(8); alias s2 : std_logic is Instruction(0); signal not_d : std_logic; signal BC : Command_vector_pc_type; signal BNC : Command_vector_pc_type; signal BN : Command_vector_pc_type; signal BNN : Command_vector_pc_type; signal BOV : Command_vector_pc_type; signal BNOV : Command_vector_pc_type; signal BZ : Command_vector_pc_type; signal BNZ : Command_vector_pc_type; begin not_d <= '1' when Instruction(9) = '0' else '0'; BC <= branch_con when Status(1) = '1' else increment; BNC <= branch_con when Status(1) = '0' else increment; BN <= branch_con when Status(4) = '1' else increment; BNN <= branch_con when Status(4) = '0' else increment; BOV <= branch_con when Status(3) = '1' else increment; BNOV <= branch_con when Status(3) = '0' else increment; BZ <= branch_con when Status(2) = '1' else increment; BNZ <= branch_con when Status(2) = '0' else increment; control : process(Instruction, Status, second_inst_ide, not_d, BC, BNC, BN, BNN, BOV, BNOV, BZ, BNZ) begin case Instruction(15 downto 12) is when "0000" => -- class 0 case Instruction(11 downto 10) is when "00" => -- class 0:0 case Instruction(9) is when '1' => -- MULWF Command_vector_opu <= NOP; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= disabled; load_FREG <= enabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= enabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when others => case Instruction(8) is when '1' => case Instruction(7 downto 4) is when "0000" => -- MOVLB Command_vector_opu <= NOP; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= enabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when others => -- NOP Command_vector_opu <= NOP; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; end case; when others => case Instruction(7 downto 0) is when "00000100" => -- CLRWDT Command_vector_opu <= NOP; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= enabled; -- table_read <= disabled; -- INDFx <= disabled; when "00000111" => -- DAW Command_vector_opu <= DAW; Command_vector_pc <= increment; Command_status <= C; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= enabled; WREG_write_enable <= enabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when "00000110" => -- POP Command_vector_opu <= NOP; Command_vector_pc <= POP; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when "00000101" => -- PUSH Command_vector_opu <= NOP; Command_vector_pc <= PUSH; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when "00000011" => -- SLEEP Command_vector_opu <= NOP; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= enabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when "00001000" => -- TBLRD* Command_vector_opu <= NOP; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= enabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= enabled; -- INDFx <= disabled; when "00001001" => -- TBLRD*+ Command_vector_opu <= NOP; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= enabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= enabled; -- INDFx <= disabled; when "00001010" => -- TBLRD*- Command_vector_opu <= NOP; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= enabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= enabled; -- INDFx <= disabled; when "00001011" => -- TBLRD+* Command_vector_opu <= NOP; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= enabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= enabled; -- INDFx <= disabled; when "11111111" => -- RESET Command_vector_opu <= NOP; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= enabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when "00010000" => -- RETFIE Command_vector_opu <= NOP; Command_vector_pc <= retur_n; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= s2&'1'; nop_enable <= enabled; -- retfie <= enabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when "00010001" => -- RETFIE Command_vector_opu <= NOP; Command_vector_pc <= retur_n; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= s2&'1'; nop_enable <= enabled; -- retfie <= enabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when "00010010" => -- RETURN Command_vector_opu <= NOP; Command_vector_pc <= retur_n; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= s2&'1'; nop_enable <= enabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when "00010011" => -- RETURN Command_vector_opu <= NOP; Command_vector_pc <= retur_n; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= s2&'1'; nop_enable <= enabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when others => -- NOP Command_vector_opu <= NOP; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; end case; end case; end case; when "01" => -- DECF Command_vector_opu <= DECF; Command_vector_pc <= increment; Command_status <= allv; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= d; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= not_d; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when "10" => -- class 0:2 case Instruction(9 downto 8) is when "00" => -- SUBLW Command_vector_opu <= SUBWF; Command_vector_pc <= increment; Command_status <= allv; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= enabled; bit_op_enable <= disabled; literal_enable <= enabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when "01" => -- IORLW Command_vector_opu <= IORWF; Command_vector_pc <= increment; Command_status <= ZN; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= enabled; bit_op_enable <= disabled; literal_enable <= enabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when "10" => -- XORLW Command_vector_opu <= XORWF; Command_vector_pc <= increment; Command_status <= ZN; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= enabled; bit_op_enable <= disabled; literal_enable <= enabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when others => -- ANDLW Command_vector_opu <= ANDWF; Command_vector_pc <= increment; Command_status <= ZN; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= enabled; bit_op_enable <= disabled; literal_enable <= enabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; end case; when others => case Instruction(9 downto 8) is when "00" => -- RETLW Command_vector_opu <= MOVF; Command_vector_pc <= retur_n; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= enabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= enabled; bit_op_enable <= disabled; literal_enable <= enabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when "01" => -- MULLW Command_vector_opu <= NOP; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= enabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= enabled; MUL_enable <= enabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when "10" => -- MOVLW Command_vector_opu <= MOVF; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= enabled; bit_op_enable <= disabled; literal_enable <= enabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when others => -- ADDLW Command_vector_opu <= ADDWF; Command_vector_pc <= increment; Command_status <= allv; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= enabled; bit_op_enable <= disabled; literal_enable <= enabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; end case; end case; when "0001" => -- class 1 case Instruction(11 downto 10) is when "00" => -- IORWF Command_vector_opu <= IORWF; Command_vector_pc <= increment; Command_status <= ZN; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= d; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= not_d; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when "01" => -- ANDWF Command_vector_opu <= ANDWF; Command_vector_pc <= increment; Command_status <= ZN; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= d; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= not_d; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when "10" => -- XORWF Command_vector_opu <= XORWF; Command_vector_pc <= increment; Command_status <= ZN; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= d; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= not_d; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when others => -- COMF Command_vector_opu <= COMF; Command_vector_pc <= increment; Command_status <= ZN; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= d; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= not_d; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; end case; when "0010" => -- class 2 case Instruction(11 downto 10) is when "00" => -- ADDWFC Command_vector_opu <= ADDWFC; Command_vector_pc <= increment; Command_status <= allv; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= d; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= not_d; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when "01" => -- ADDWF Command_vector_opu <= ADDWF; Command_vector_pc <= increment; Command_status <= allv; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= d; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= not_d; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when "10" => -- INCF Command_vector_opu <= INCF; Command_vector_pc <= increment; Command_status <= allv; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= d; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= not_d; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when others => -- DECFSZ Command_vector_opu <= DECF; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= SZ; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= d; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= not_d; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; end case; when "0011" => -- class 3 case Instruction(11 downto 10) is when "00" => -- RRCF Command_vector_opu <= RRCF; Command_vector_pc <= increment; Command_status <= CZN; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= d; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= not_d; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when "01" => -- RLCF Command_vector_opu <= RLCF; Command_vector_pc <= increment; Command_status <= CZN; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= d; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= not_d; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when "10" => -- SWAPF Command_vector_opu <= SWAPF; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= d; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= not_d; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when others => -- INCFSZ Command_vector_opu <= INCF; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= SZ; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= d; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= not_d; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; end case; when "0100" => -- class 4 case Instruction(11 downto 10) is when "00" => -- RRNCF Command_vector_opu <= RRNCF; Command_vector_pc <= increment; Command_status <= ZN; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= d; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= not_d; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when "01" => -- RLNCF Command_vector_opu <= RLNCF; Command_vector_pc <= increment; Command_status <= ZN; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= d; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= not_d; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when "10" => -- INFSNZ Command_vector_opu <= INCF; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= SNZ; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= d; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= not_d; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when others => -- DCFSNZ Command_vector_opu <= DECF; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= SNZ; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= d; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= not_d; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; end case; when "0101" => -- class 5 case Instruction(11 downto 10) is when "00" => -- MOVF Command_vector_opu <= MOVF; Command_vector_pc <= increment; Command_status <= ZN; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= d; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= not_d; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when "01" => -- SUBFWB Command_vector_opu <= SUBFWB; Command_vector_pc <= increment; Command_status <= allv; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= d; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= not_d; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when "11" => -- SUBWF Command_vector_opu <= SUBWF; Command_vector_pc <= increment; Command_status <= allv; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= d; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= not_d; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when others => -- SUBWFB Command_vector_opu <= SUBWFB; Command_vector_pc <= increment; Command_status <= allv; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= d; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= not_d; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; end case; when "0110" => -- class 6 case Instruction(11 downto 9) is when "101" => -- CLRF Command_vector_opu <= CLRF; Command_vector_pc <= increment; Command_status <= Z; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= enabled; load_FREG <= disabled; read_result <= enabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when "001" => -- CPFSEQ Command_vector_opu <= CPF; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= CPFSEQ; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= disabled; load_FREG <= enabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when "010" => -- CPFSGT Command_vector_opu <= CPF; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= CPFSGT; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= disabled; load_FREG <= enabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when "000" => -- CPFSLT Command_vector_opu <= CPF; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= CPFSLT; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= disabled; load_FREG <= enabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when "111" => -- MOVWF Command_vector_opu <= MOVWF; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= enabled; load_FREG <= disabled; read_result <= enabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when "110" => -- NEGF Command_vector_opu <= NEGF; Command_vector_pc <= increment; Command_status <= allv; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= enabled; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when "100" => -- SETF Command_vector_opu <= SETF; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= enabled; load_FREG <= disabled; read_result <= enabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when others => -- TSTFSZ Command_vector_opu <= MOVF; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= SZ; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= disabled; load_FREG <= enabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; end case; when "0111" => -- BTG Command_vector_opu <= BTG; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= enabled; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= disabled; bit_op_enable <= enabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; -- table_read <= disabled; clear_watchdog <= disabled; -- INDFx <= enabled; when "1000" => -- BSF Command_vector_opu <= BSF; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= enabled; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= disabled; bit_op_enable <= enabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when "1001" => -- BCF Command_vector_opu <= BCF; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= enabled; load_FREG <= enabled; read_result <= enabled; WREG_write_enable <= disabled; bit_op_enable <= enabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when "1010" => -- BTFSS Command_vector_opu <= BTF; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= BTFSS; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= disabled; load_FREG <= enabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= enabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when "1011" => -- BTFSC Command_vector_opu <= BTF; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= BTFSC; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= disabled; load_FREG <= enabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= enabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when "1100" => -- MOVFF Command_vector_opu <= NOP; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_MOVFF; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= enabled; write_D <= disabled; load_FREG <= enabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= enabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when "1101" => -- class 13 case Instruction(11) is when '0' => -- BRA Command_vector_opu <= NOP; Command_vector_pc <= branch_inc; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= enabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when others => -- RCALL Command_vector_opu <= NOP; Command_vector_pc <= RCALL; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= enabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; end case; when "1110" => -- class 14 case Instruction(11 downto 8) is when "0010" => -- BC Command_vector_opu <= NOP; Command_vector_pc <= BC; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= BC(2); -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when "0110" => -- BN Command_vector_opu <= NOP; Command_vector_pc <= BN; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= BN(2); -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when "0011" => -- BNC Command_vector_opu <= NOP; Command_vector_pc <= BNC; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= BNC(2); -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when "0111" => -- BNN Command_vector_opu <= NOP; Command_vector_pc <= BNN; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= BNN(2); -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when "0101" => -- BNOV Command_vector_opu <= NOP; Command_vector_pc <= BNOV; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= BNOV(2); -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when "0001" => -- BNZ Command_vector_opu <= NOP; Command_vector_pc <= BNZ; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= BNZ(2); -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when "0100" => -- BOV Command_vector_opu <= NOP; Command_vector_pc <= BOV; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= BOV(2); -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when "0000" => -- BZ Command_vector_opu <= NOP; Command_vector_pc <= BZ; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= BZ(2); -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when "1100" => -- CALL Command_vector_opu <= NOP; Command_vector_pc <= CALL1; Command_status <= none; second_inst_inf <= sec_CALL; Skip_inf <= not_skip; call_return <= s1&'0'; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when "1101" => -- CALL Command_vector_opu <= NOP; Command_vector_pc <= CALL1; Command_status <= none; second_inst_inf <= sec_CALL; Skip_inf <= not_skip; call_return <= s1&'0'; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when "1111" => -- GOTO Command_vector_opu <= NOP; Command_vector_pc <= GOTO1; Command_status <= none; second_inst_inf <= sec_GOTO; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when "1110" => case Instruction(7 downto 6) is when "00" => -- LFSR Command_vector_opu <= NOP; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; --sec_LFSRx; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= enable_1stcyc; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when others => -- NOP Command_vector_opu <= NOP; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; end case; when others => -- NOP Command_vector_opu <= NOP; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; end case; when others => -- class 15 case second_inst_ide is when "100" => -- 2nd MOVFF Command_vector_opu <= MOVF; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= enabled; load_FREG <= disabled; read_result <= enabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= enabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= enabled; when "101" => -- 2nd LFSR Command_vector_opu <= NOP; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= enable_2ndcyc; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when "110" => -- 2nd GOTO Command_vector_opu <= NOP; Command_vector_pc <= GOTO2; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when "111" => -- 2nd CALL Command_vector_opu <= NOP; Command_vector_pc <= CALL2; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; when others => -- NOP Command_vector_opu <= NOP; Command_vector_pc <= increment; Command_status <= none; second_inst_inf <= sec_disable; Skip_inf <= not_skip; call_return <= none_action; nop_enable <= disabled; -- retfie <= disabled; read_D <= disabled; write_D <= disabled; load_FREG <= disabled; read_result <= disabled; WREG_write_enable <= disabled; bit_op_enable <= disabled; literal_enable <= disabled; MUL_enable <= disabled; MOVFF_enable <= disabled; -- load_FSRx <= load_disable; load_BSR <= disabled; soft_reset_enable <= disabled; sleep_mode_enable <= disabled; clear_watchdog <= disabled; -- table_read <= disabled; -- INDFx <= disabled; end case; end case; end process; end Decode;