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-- Company:        Ferhat Abbas University - Algeria
-- Engineer:       Ibrahim MEZZAH
-- Progect Supervisor: Dr H. Chemali
-- Create Date:    00:56:38 06/04/05
-- Design Name:    Instruction decoder and control
-- Module Name:    InstructionDecoder_Control - Decode_Cotrol
-- Project Name:   Microcontroller IP (MCIP)
-- Target Device:  xc3s500e-4fg320
-- Tool versions:  Xilinx ISE 9.1.03i
-- Description:	 Decodes the fetched instruction and selects the block
--                 concernrd by read and write operations.
-- Revision: 		 07/07/2008
-- Revision  2.2 - Add description
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity Instruction_Decoder is
    Port ( nreset            : in std_logic;
			  Q1                : in std_logic;
			  Q4                : in std_logic;
			  Fetched_instruction : in std_logic_vector(15 downto 0);
			  Data_add          : in std_logic_vector(11 downto 0);
			  New_status        : in std_logic_vector(4 downto 0);
			  Set_response      : in std_logic_vector(1 downto 0);
			  Data              : inout std_logic_vector(7 downto 0);
 
			  Command_vector_opu : out std_logic_vector(13 downto 0);
			  Command_vector_pc : out std_logic_vector(6 downto 0);
			  Command_status    : out std_logic_vector(4 downto 0);
			  Current_status    : out std_logic_vector(4 downto 0);
			  Bit_op            : out std_logic_vector(2 downto 0);
			  call_return       : out std_logic_vector(1 downto 0);
			  IR11_0            : out std_logic_vector(11 downto 0);
			  r_w_ram           : out std_logic_vector(1 downto 0);
			  r_w_add_pr        : out std_logic_vector(1 downto 0);
			  r_w_opu            : out std_logic_vector(1 downto 0);
			  r_w_port          : out std_logic_vector(1 downto 0);
			  r_w_wdt           : out std_logic_vector(1 downto 0);
			  bit_op_enable     : out std_logic;
			  load_FREG         : out std_logic;
			  read_result       : out std_logic;
			  WREG_write_enable : out std_logic;
			  MUL_enable        : out std_logic;
			  MOVFF_enable      : out std_logic;
			  load_BSR          : out std_logic;
			  soft_reset_enable : out std_logic;
			  sleep_mode_enable : out std_logic;
			  clear_watchdog    : out std_logic
);
end Instruction_Decoder;
 
architecture Decode_Control of Instruction_Decoder is
 
component Decoder
    Port ( Instruction       : in std_logic_vector(15 downto 0);
			  Status            : in std_logic_vector(4 downto 1);
			  second_inst_ide   : in std_logic_vector(2 downto 0);
			  Command_vector_pc : out std_logic_vector(6 downto 0);
			  Command_vector_opu : out std_logic_vector(13 downto 0);
			  Command_status    : out std_logic_vector(4 downto 0);
			  second_inst_inf   : out std_logic_vector(2 downto 0);
			  Skip_inf          : out std_logic_vector(4 downto 0);
			  read_write        : out std_logic_vector(1 downto 0);
			  call_return       : out std_logic_vector(1 downto 0);
			  bit_op_enable     : out std_logic;
			  load_FREG         : out std_logic;
			  read_result       : out std_logic;
			  WREG_write_enable : out std_logic;
			  MUL_enable        : out std_logic;
			  MOVFF_enable      : out std_logic;
			  load_BSR          : out std_logic;
			  nop_enable        : out std_logic;
			  soft_reset_enable : out std_logic;
			  sleep_mode_enable : out std_logic;
			  clear_watchdog    : out std_logic;
			  literal_enable    : out std_logic );
end component Decoder;
 
--component Instruction_Control
--    Port ( nreset             : in std_logic;
--           Q1                 : in std_logic;
--           Fetched_instruction  : in std_logic_vector(15 downto 0);
--           Set_response       : in std_logic_vector(1 downto 0);
--           Skip_info          : in std_logic_vector(4 downto 0);
--           nop_enable         : in std_logic;
--           retfie             : in std_logic;
--           INTH               : in std_logic;
--           INTL               : in std_logic;
--           GIEH               : in std_logic;
--           GIEL               : in std_logic;
--           second_inst_enable : in std_logic;
--           freeze_enable      : out std_logic;
--           GIEHout            : out std_logic;
--           GIELout            : out std_logic;
--           load_INTCON        : out std_logic;
--           Instruction        : out std_logic_vector(15 downto 0) );
--end component Instruction_Control;
 
component Selection_block
    Port ( R_W        : in std_logic_vector(1 downto 0);
	 		  Address    : in  std_logic_vector(11 downto 0);
			  r_w_ram    : out std_logic_vector(1 downto 0);
			  r_w_add_pr : out std_logic_vector(1 downto 0);
			  r_w_opu    : out std_logic_vector(1 downto 0);
			  r_w_port   : out std_logic_vector(1 downto 0);
			  r_w_dec    : out std_logic_vector(1 downto 0);
			  r_w_wdt    : out std_logic_vector(1 downto 0) );
end component Selection_block;
 
--component Interrupt_Block
--    Port ( INTCON  : in std_logic_vector(7 downto 0);
--           INTCON2 : in std_logic_vector(7 downto 0);
--           INTCON3 : in std_logic_vector(1 downto 0);
--           INTH    : out std_logic;
--           INTL    : out std_logic;
--           wake_up : out std_logic);
--end component Interrupt_Block;
 
  signal data_read  : std_logic_vector(7 downto 0);
 
  signal IR : std_logic_vector(15 downto 0);
  signal instruction : std_logic_vector(15 downto 0);
 
  signal STATUS      : std_logic_vector(4 downto 0);
  signal STATUSs     : std_logic_vector(4 downto 0);
  signal STATUSmap   : std_logic_vector(4 downto 1);
 
  signal literal_enable : std_logic;
  signal nop_enable     : std_logic;
  signal sleep_mode_enables : std_logic;
 
  signal Set_response_register : std_logic_vector(1 downto 0);
  signal Command_status_s      : std_logic_vector(4 downto 0);
 
  signal R_W     : std_logic_vector(1 downto 0);
  signal r_w_dec : std_logic_vector(1 downto 0);
 
  signal second_inst_register  : std_logic_vector(2 downto 0);
  signal second_inst_inf       : std_logic_vector(2 downto 0);
  signal Skip_inf      : std_logic_vector(4 downto 0);
  signal call_returns          : std_logic_vector(1 downto 0);
 
  signal nop_enables : std_logic;
 
  alias read_en    : std_logic is r_w_dec(1);
  alias write_en   : std_logic is r_w_dec(0);
 
 
begin
 
ins_decoder : Decoder
Port map ( Instruction       => IR,
			  Status            => STATUSmap,
			  second_inst_ide   => second_inst_register,
			  Command_vector_pc => Command_vector_pc,
			  Command_vector_opu => Command_vector_opu,
			  Command_status    => Command_status_s,
			  second_inst_inf   => second_inst_inf,
			  Skip_inf          => Skip_inf,
			  read_write        => R_W,
			  call_return       => call_returns,
			  bit_op_enable     => bit_op_enable,
			  load_FREG         => load_FREG,
			  read_result       => read_result,
			  WREG_write_enable => WREG_write_enable,
			  MUL_enable        => MUL_enable,
			  MOVFF_enable      => MOVFF_enable,
			  load_BSR          => load_BSR,
			  nop_enable        => nop_enable,
			  soft_reset_enable => soft_reset_enable,
			  sleep_mode_enable => sleep_mode_enables,
			  clear_watchdog    => clear_watchdog,
			  literal_enable    => literal_enable );
 
 
selecter : Selection_Block
Port map ( R_W        => R_W,
	 		  Address    => Data_add,
			  r_w_ram    => r_w_ram,
			  r_w_add_pr => r_w_add_pr,
			  r_w_opu    => r_w_opu,
			  r_w_port   => r_w_port,
			  r_w_dec    => r_w_dec,
			  r_w_wdt    => r_w_wdt );
 
 
	nop_enables <= '1'		when (nop_enable = '1' or (Skip_inf(4) = '1' and
				(Skip_inf(3 downto 2)=(Skip_inf(1 downto 0) and Set_response_register)))) else
						'0';
 
	instruction <= X"F000" when nop_enables = '1' else Fetched_instruction;
 
 
	data_read <= IR(7 downto 0)				when literal_enable='1' else
					 "000"&STATUS;
	Data <= data_read					when (read_en='1' or literal_enable='1')and Q1='1'else
			  (others => 'Z');
	sleep_mode_enable <= sleep_mode_enables;
	Command_status <= Command_status_s;
	STATUSmap      <= STATUS(4 downto 2)&STATUS(0);
	Current_status <= STATUS;
	Bit_op      <= IR(11 downto 9);
	call_return <= call_returns;
	IR11_0      <= IR(11 downto 0);
 
 
	process(nreset, Q1, instruction, second_inst_inf)
		begin
		  if nreset = '0' then
			 IR <= (others => '0');
			 second_inst_register <= (others => '0');
		  else
			 if Q1'event and Q1 = '1' then
			 	IR <= instruction;
				second_inst_register <= second_inst_inf;
			 end if;
		  end if;
		end process;
 
	process(nreset, Q4, write_en, Data,
			  Set_response, call_returns, STATUS, STATUSs)
		begin
		  if nreset = '0' then
			 STATUS  <= (others => '0');
			 STATUSs <= (others => '0');
			 Set_response_register <= (others => '0');
		  else
			 if Q4'event and Q4 = '1' then
				Set_response_register <= Set_response;
				if write_en = '1' and Command_status_s = "00000" then
					STATUS <= Data(4 downto 0);
				else
				  if call_returns(1) = '1' then
					if call_returns(0) = '0' then
					  STATUSs <= STATUS;				-- call
					else
					  STATUS  <= STATUSs;			-- return
					end if;
				  else
					  STATUS  <= New_status;
				  end if;
				end if;
			 end if;
		  end if;
		end process;
 
end Decode_Control;