Subversion Repositories mcip_open

NET "clk50MHz" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
# Define clock period for 50 MHz oscillator
NET "clk50MHz" PERIOD = 20.0ns HIGH 40%;

NET "reset" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
#NET "clock_out" LOC = D7;

NET "PORTB[7]" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "PORTB[6]" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "PORTB[5]" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "PORTB[4]" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "PORTB[3]" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "PORTB[2]" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "PORTB[1]" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "PORTB[0]" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "PORTA[0]" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "PORTA[1]" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "PORTA[2]" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
NET "PORTA[3]" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;

NET "PORTC[4]" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "PORTC[5]" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "PORTC[6]" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "PORTC[7]" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

NET "PORTD[7]" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "PORTD[6]" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "PORTD[5]" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

#NET "PORTA[7]" LOC = C5;
#NET "PORTA[6]" LOC = D5;
#NET "PORTA[5]" LOC = A4;
#NET "PORTA[4]" LOC = B4;

#NET "PORTC[3]" LOC = F7;
#NET "PORTC[2]" LOC = E7;
#NET "PORTC[1]" LOC = B6;
#NET "PORTC[0]" LOC = A6;

#NET "PORTD[4]" LOC = A13;
#NET "PORTD[3]" LOC = B13;
#NET "PORTD[2]" LOC = A14;
#NET "PORTD[1]" LOC = B14;
#NET "PORTD[0]" LOC = C14;