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[/] [mcip_open/] [trunk/] [MCIPopen_XilinxISEproject/] [LCDapp_MCIPopen.vhd] - Rev 4
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---------------------------------------------------------------------------------- -- Company: Ferhat Abbas University - Algeria -- Engineer: Ibrahim MEZZAH -- -- Create Date: 08:17:48 07/25/2015 -- Design Name: MCIP open -- Module Name: LCDapp_MCIPopen - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity LCDapp_MCIPopen is Generic ( STKPTR_length : integer := 5; -- Stack Pointer Length --> min = 2, max = 5 STVREN : std_logic := '1'; -- Stack Overflow/Underflow Reset Enable bit WDTPS : std_logic_vector(3 downto 0) := "0100"; -- Watchdog Timer Postscale Select bits WDTEN : std_logic := '0'; -- Watchdog Timer enable bit Banks_number : integer := 3; -- number of banks, min = 2, max = 16 dm_TOPaddr : std_logic_vector(11 downto 0) := x"2FF"; IAlength : integer := 12; -- min = 2, max = 21 pm_TOPaddr : std_logic_vector(20 downto 0) := '0'&x"03FFF" ); Port ( reset : in std_logic; clk50MHz : in std_logic; direction : in std_logic; -- must be always '0' clock_out : out std_logic; PORTA : in std_logic_vector(7 downto 0); PORTB : out std_logic_vector(7 downto 0); PORTC : out std_logic_vector(7 downto 0); PORTD : out std_logic_vector(7 downto 0) ); end LCDapp_MCIPopen; architecture Behavioral of LCDapp_MCIPopen is signal clk25MHz : std_logic := '1'; signal nreset : std_logic := '1'; signal PORTAs : std_logic_vector(7 downto 0); signal PORTBs : std_logic_vector(7 downto 0); signal PORTCs : std_logic_vector(7 downto 0); signal PORTDs : std_logic_vector(7 downto 0); begin MCU: entity work.MCIPopen_mcu_example Generic map( STKPTR_length => STKPTR_length, STVREN => STVREN, WDTPS => WDTPS, WDTEN => WDTEN, Banks_number => Banks_number, dm_TOPaddr => dm_TOPaddr, IAlength => IAlength, pm_TOPaddr => pm_TOPaddr ) Port map ( nreset => nreset, clk25MHz => clk25MHz, Wdt_clock => clk25MHz, clock_out => clock_out, PORTA => PORTAs, PORTB => PORTBs, PORTC => PORTCs, PORTD => PORTDs); CLOCKpros : process(clk50MHz) begin if clk50MHz'event and clk50MHz = '1' then clk25MHz <= not clk25MHz; end if; end process; nreset <= not reset; PORTAs <= PORTA when direction = '0' else "ZZZZZZZZ"; PORTB <= PORTBs; PORTBs <= x"00" when direction = '1' else "ZZZZZZZZ"; PORTC <= PORTCs; PORTCs <= x"00" when direction = '1' else "ZZZZZZZZ"; PORTD <= PORTDs; PORTDs <= x"00" when direction = '1' else "ZZZZZZZZ"; end Behavioral;