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[/] [mcip_open/] [trunk/] [MCIPopen_XilinxISEproject/] [MCIPopen.vhd] - Rev 4
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-------------------------------------------------------------------------------- -- Company: Ferhat Abbas University - Algeria -- Engineer: Ibrahim MEZZAH -- Progect Supervisor: Dr H. Chemali -- Create Date: july 2015 -- Design Name: MCIP open -- Module Name: MCIPopen -- Project Name: Microcontroller IP (MCIP) -- Target Device: xc3s500e-4fg320 -- Tool versions: Xilinx ISE 14 -- Description: "MCIP open" is a light vertion of MCIP core, it is compatible -- whith Microchip PIC18 microcontrolle. -- Revision: -- Revision 0 -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity MCIPopen is Generic ( STKPTR_length : integer := 5; -- Stack Pointer Length -- < 6 STVREN : std_logic := '1'; -- Stack Overflow/Underflow Reset Enable bit WDTPS : std_logic_vector(3 downto 0) := "0100"; -- Watchdog Timer Postscale Select bits WDTEN : std_logic := '0'); -- Watchdog Timer enable bit Port ( nreset : in std_logic; clock : in std_logic; Wdt_clock : in std_logic; Instruction : in std_logic_vector(15 downto 0); clock_out : out std_logic; nresetDevice : out std_logic; Q1 : out std_logic; Q4 : out std_logic; RE_ram : out std_logic; WE_ram : out std_logic; Istruction_address : out std_logic_vector(20 downto 0); Data_address : out std_logic_vector(11 downto 0); Data_Bus : inout std_logic_vector(7 downto 0); PORTA : inout std_logic_vector(7 downto 0); PORTB : inout std_logic_vector(7 downto 0); PORTC : inout std_logic_vector(7 downto 0); PORTD : inout std_logic_vector(7 downto 0) ); end MCIPopen; architecture mapping of MCIPopen is component CPU Generic ( STKPTR_length : integer := 5; STVREN : std_logic := '1'); Port ( nreset : in std_logic; Q : in std_logic_vector(1 to 4); Instruction : in std_logic_vector(15 downto 0); DATA : inout std_logic_vector(7 downto 0); Istruction_address : out std_logic_vector(20 downto 0); Data_address : out std_logic_vector(11 downto 0); address_latch_port : out std_logic_vector(3 downto 0); r_w_ram : out std_logic_vector(1 downto 0); r_w_port : out std_logic_vector(1 downto 0); r_w_wdt : out std_logic_vector(1 downto 0); soft_reset_enable : out std_logic; sleep_mode_enable : out std_logic; clear_watchdog : out std_logic; stack_overflow : out std_logic ); end component CPU; component PORTs Port ( nreset : in std_logic; Q1 : in std_logic; Q4 : in std_logic; RE : in std_logic; WE : in std_logic; SFRs_Address : in std_logic_vector(3 downto 0); DATA : inout std_logic_vector(7 downto 0); PORTA : inout std_logic_vector(7 downto 0); PORTB : inout std_logic_vector(7 downto 0); PORTC : inout std_logic_vector(7 downto 0); PORTD : inout std_logic_vector(7 downto 0)); end component PORTs; component reset_module Port ( clock : in std_logic; nExternal_reset : in std_logic; Soft_reset : in std_logic; WDT_reset : in std_logic; Stack_reset : in std_logic; nreset : out std_logic); end component reset_module; component PLL Port ( clock : in std_logic; nreset : in std_logic; IDLEN : in std_logic; Sleep_mode_enable : in std_logic; Q1 : out std_logic; Q2 : out std_logic; Q3 : out std_logic; Q4 : out std_logic; internal_clock : out std_logic); end component PLL; component Watchdog Generic(WDTPS : std_logic_vector(3 downto 0) := "0100"; WDTEN : std_logic := '0'); Port ( nreset : in std_logic; WDT_clock : in std_logic; Q1 : in std_logic; Q4 : in std_logic; RE : in std_logic; WE : in std_logic; clrWDT : in std_logic; Sleep : in std_logic; DATA : inout std_logic_vector(7 downto 0); WDT_reset : out std_logic; WDTwake_up : out std_logic); end component Watchdog; signal Q : std_logic_vector(1 to 4); signal address_latch_port : std_logic_vector(3 downto 0); signal r_w_port : std_logic_vector(1 downto 0); signal r_w_wdt : std_logic_vector(1 downto 0); signal r_w_ram : std_logic_vector(1 downto 0); signal soft_reset_enable : std_logic; signal sleep_mode_enable : std_logic; signal sleep_mode : std_logic; signal clear_watchdog : std_logic; signal WDTwake_up : std_logic; signal WDT_reset : std_logic; signal stack_overflow : std_logic; signal nreset_device : std_logic; signal clock_div4 : std_logic; begin CPU_block : CPU Generic map( STKPTR_length => STKPTR_length, STVREN => STVREN) Port map ( nreset => nreset_device, Q => Q, Instruction => Instruction, DATA => DATA_BUS, Istruction_address => Istruction_address, Data_address => Data_address, address_latch_port => address_latch_port, r_w_ram => r_w_ram, r_w_port => r_w_port, r_w_wdt => r_w_wdt, soft_reset_enable => soft_reset_enable, sleep_mode_enable => sleep_mode_enable, clear_watchdog => clear_watchdog, stack_overflow => stack_overflow ); Ports_block : PORTs Port map ( nreset => nreset_device, Q1 => Q(1), Q4 => Q(4), RE => r_w_port(1), WE => r_w_port(0), SFRs_Address => address_latch_port, DATA => DATA_BUS, PORTA => PORTA, PORTB => PORTB, PORTC => PORTC, PORTD => PORTD); Reset_u: reset_module Port map ( clock => clock, nExternal_reset => nreset, Soft_reset => soft_reset_enable, WDT_reset => WDT_reset, Stack_reset => stack_overflow, nreset => nreset_device); PLL_u: PLL Port map ( clock => clock, nreset => nreset_device, IDLEN => '0', Sleep_mode_enable => sleep_mode, Q1 => Q(1), Q2 => Q(2), Q3 => Q(3), Q4 => Q(4), internal_clock => clock_div4); Watchdog_u: Watchdog Generic map(WDTPS => WDTPS, WDTEN => WDTEN) Port map ( nreset => nreset_device, WDT_clock => Wdt_clock, Q1 => Q(1), Q4 => Q(4), RE => r_w_wdt(1), WE => r_w_wdt(0), clrWDT => clear_watchdog, Sleep => sleep_mode_enable, DATA => DATA_BUS, WDT_reset => WDT_reset, WDTwake_up => WDTwake_up); Q1 <= Q(1); Q4 <= Q(4); RE_ram <= r_w_ram(1); WE_ram <= r_w_ram(0); clock_out <= clock_div4; nresetDevice <= nreset_device; sleep_mode <= '1' when sleep_mode_enable = '1' and WDTwake_up = '0' else '0'; end mapping;