Subversion Repositories mcip_open

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:09:51 07/24/2015 
-- Design Name: 
-- Module Name:    MCIPopen_mcu_example - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
 
entity MCIPopen_mcu_example is
	 Generic (	STKPTR_length	: integer := 5;		-- Stack Pointer Length --> min = 2, max = 5
					STVREN			: std_logic := '1';	-- Stack Overflow/Underflow Reset Enable bit
 
					WDTPS : std_logic_vector(3 downto 0) := "0100"; -- Watchdog Timer Postscale Select bits
					WDTEN : std_logic := '0'; -- Watchdog Timer enable bit
 
					Banks_number		: integer := 3;	-- number of banks, min = 2, max = 16
					dm_TOPaddr			: std_logic_vector(11 downto 0) := x"2FF";
 
					IAlength 		: integer := 12; -- min = 2, max = 21
					pm_TOPaddr		: std_logic_vector(20 downto 0) := '0'&x"03FFF"
					); 							
 
    Port ( nreset             : in std_logic;
           clk25MHz           : in std_logic;
			  Wdt_clock				: in std_logic;
			  clock_out          : out std_logic;
           PORTA              : inout std_logic_vector(7 downto 0);
           PORTB              : inout std_logic_vector(7 downto 0);
           PORTC              : inout std_logic_vector(7 downto 0);
           PORTD              : inout std_logic_vector(7 downto 0) );
end MCIPopen_mcu_example;
 
architecture Behavioral of MCIPopen_mcu_example is
 
component MCIPopen is
    Generic ( STKPTR_length : integer := 5;  -- Stack Pointer Length -- < 6
				  STVREN : std_logic := '1'; 	-- Stack Overflow/Underflow Reset Enable bit
				  WDTPS : std_logic_vector(3 downto 0) := "0100"; -- Watchdog Timer Postscale Select bits
				  WDTEN : std_logic := '0'); -- Watchdog Timer enable bit
    Port ( nreset             : in std_logic;
           clock              : in std_logic;
			  Wdt_clock				: in std_logic;
           Instruction        : in std_logic_vector(15 downto 0);
			  clock_out          : out std_logic;
			  nresetDevice       : out std_logic;
			  Q1                 : out std_logic;
			  Q4                 : out std_logic;
			  RE_ram             : out std_logic;
			  WE_ram             : out std_logic;
           Istruction_address : out std_logic_vector(20 downto 0);
           Data_address       : out std_logic_vector(11 downto 0);
           Data_Bus           : inout std_logic_vector(7 downto 0);
           PORTA              : inout std_logic_vector(7 downto 0);
           PORTB              : inout std_logic_vector(7 downto 0);
           PORTC              : inout std_logic_vector(7 downto 0);
           PORTD              : inout std_logic_vector(7 downto 0) );
end component MCIPopen;
 
 
component Data_Memory_Banks_Controller is
	 Generic (Banks_number		: integer := Banks_number;	-- number of banks, min = 2, max = 16
				 dm_TOPaddr			: std_logic_vector(11 downto 0) := dm_TOPaddr);
    Port ( RE						: in std_logic;
           WE						: in std_logic;
			  Data_address			: in std_logic_vector(11 downto 0);
--           DATA					: inout std_logic_vector(7 downto 0);
 
           RE_bank				: out std_logic;
           WE_bank				: out std_logic;
           Bank_selection		: out std_logic_vector(0 to Banks_number-1);
           Bank_data_address	: out std_logic_vector(7 downto 0)
--           Bank_data			: inout std_logic_vector(7 downto 0)
			  );
end component Data_Memory_Banks_Controller;
 
component Memory_bank is
    Port ( Address : in std_logic_vector(7 downto 0);
           enable  : in std_logic;
           RE      : in std_logic;
			  WE      : in std_logic;
           Q1      : in std_logic;
           Q4      : in std_logic;
           DATA    : inout std_logic_vector(7 downto 0));
end component Memory_bank;
 
component Program_Memory_Controller is
	 Generic (IAlength 		: integer := IAlength; -- min = 2, max = 21
				 pm_TOPaddr		: std_logic_vector(20 downto 0) := pm_TOPaddr);
    Port ( Prg_addr			: in std_logic_vector(20 downto 0);
			  Instruction		: out std_logic_vector(15 downto 0);
 
			  eff_Prg_addr		: out std_logic_vector(IAlength-1 downto 0);
			  Prg_memory_bus	: in std_logic_vector(15 downto 0));
end component Program_Memory_Controller;
 
component Program_Memory is
	 Generic (IAlength 		: integer := IAlength);  -- Instruction Address Length -- min = 2, max = 21
    Port ( Address : in std_logic_vector(IALength-1 downto 0);
           nreset  : in std_logic;
           Q1      : in std_logic;
           Instruction : out std_logic_vector(15 downto 0));
end component Program_Memory;
 
--	signal clk_2				: std_logic;
--	signal clk_3				: std_logic_vector(1 downto 0);
 
	signal mcu_nreset			: std_logic;
--	signal internal_clock	: std_logic;
	signal Q1					: std_logic;
	signal Q4					: std_logic;
 
--	signal Data_addr			: std_logic_vector(11 downto 0);
	signal Data_bus			: std_logic_vector(7 downto 0);
--	signal mcu_RE				: std_logic;
--	signal mcu_WE				: std_logic;
 
--	signal RE_intr_con		: std_logic;
--	signal WE_intr_con		: std_logic;
--	signal SFR_address_intr_con: std_logic_vector(4 downto 0);
 
	signal Prg_addr			: std_logic_vector(20 downto 0);
	signal Inst_bus			: std_logic_vector(15 downto 0);
 
	signal eff_Prg_addr		: std_logic_vector(IAlength-1 downto 0);
	signal Prg_memory_bus	: std_logic_vector(15 downto 0);
 
--	signal enable_sleep		: std_logic;
--	signal WDTwake_up			: std_logic;
--	signal sleep_enabled		: std_logic;
 
--	signal INTH					: std_logic;
--	signal INTL					: std_logic;
--	signal GIE					: std_logic;
--	signal GIEL					: std_logic;
--	signal GIEHfeedback		: std_logic;
--	signal GIELfeedback		: std_logic;
--	signal load_INTCON		: std_logic;
--	signal IPEN					: std_logic;
--
--	signal Interrupt			: std_logic_vector(1 to Intr_Nbr);
--	signal Interrupt_ack		: std_logic_vector(1 to Intr_Nbr);
--
--	signal PORTC_addr			: std_logic_vector(3 downto 0);
--	signal RE_PORTC			: std_logic;
--	signal WE_PORTC			: std_logic;
--
--	signal PORTD_addr			: std_logic_vector(3 downto 0);
--	signal RE_PORTD			: std_logic;
--	signal WE_PORTD			: std_logic;
--
--	signal Timer2_addr		: std_logic_vector(1 downto 0);
--	signal RE_Timer2			: std_logic;
--	signal WE_Timer2			: std_logic;
 
	signal Data_memory_addr	: std_logic_vector(11 downto 0);
	signal RE_data_memory	: std_logic;
	signal WE_data_memory	: std_logic;
 
	signal RE_bank			: std_logic;
	signal WE_bank			: std_logic;
	signal Bank_selection	: std_logic_vector(0 to Banks_number-1);
	signal Bank_data_address	: std_logic_vector(7 downto 0);
--	signal Bank_data			: std_logic_vector(7 downto 0);
 
 
 
begin
 
MCIPcore : MCIPopen
Generic map ( STKPTR_length => STKPTR_length,
				  STVREN => STVREN,
				  WDTPS => WDTPS,
				  WDTEN => WDTEN)
Port map ( nreset             => nreset,
           clock              => clk25MHz,
			  Wdt_clock				=> Wdt_clock,
           Instruction        => Inst_bus,
			  clock_out          => clock_out,
			  nresetDevice       => mcu_nreset,
			  Q1                 => Q1,
			  Q4                 => Q4,
			  RE_ram             => RE_data_memory,
			  WE_ram             => WE_data_memory,
           Istruction_address => Prg_addr,
           Data_address       => Data_memory_addr,
           Data_Bus           => Data_bus,
           PORTA              => PORTA,
           PORTB              => PORTB,
           PORTC              => PORTC,
           PORTD              => PORTD);
--Port map ( nreset					=> nreset,
--           mcu_nreset			=> mcu_nreset,
--			  
--           clk						=> clk_2,
--			  Wdt_clk				=> clk_2,
--           internal_clock		=> internal_clock,
--           Qi						=> Qi,
--			  
--			  Data_addr				=> Data_addr,
--           Data_bus				=> Data_bus,
--           RE						=> mcu_RE,
--           WE						=> mcu_WE,
--			  
--           RE_intr_con			=> RE_intr_con,
--           WE_intr_con			=> WE_intr_con,
--			  SFR_address_intr_con => SFR_address_intr_con,
--			  
--			  Prg_addr				=> Prg_addr,
--			  Inst_bus				=> Inst_bus,
--			  
--			  enable_sleep			=> enable_sleep,
--			  WDTwake_up			=> WDTwake_up,
--           sleep_enabled		=> sleep_enabled,
--			  
--			  -- Debug signals
----			  IR_register       => IR_register,
----			  Status_register   => Status_register,
----           NewStatus       => NewStatus,
----           Command_PC       => Command_PC,
--			  ----------------
--
--           INTH					=> INTH,
--           INTL					=> INTL,
--           GIE						=> GIE,
--           GIEL					=> GIEL,
--           GIEHfeedback			=> GIEHfeedback,
--           GIELfeedback			=> GIELfeedback,
--           load_INTCON			=> load_INTCON,
--           IPEN					=> IPEN
--			  );
 
-- Data and Program memories
 
Data_Memory_Controller : Data_Memory_Banks_Controller
Port map ( RE						=> RE_data_memory,
           WE						=> WE_data_memory,
			  Data_address			=> Data_memory_addr,
--           DATA					=> Data_bus,
 
           RE_bank				=> RE_bank,
           WE_bank				=> WE_bank,
           Bank_selection		=> Bank_selection,
           Bank_data_address	=> Bank_data_address
--           Bank_data			=> Bank_data
			  );
 
Memory_banks : for i in 0 to Banks_number-1 generate
	bank: Memory_bank 
Port map ( Address => Bank_data_address,
           enable  => Bank_selection(i),
           RE      => RE_bank,
			  WE      => WE_bank,
           Q1      => Q1,
           Q4      => Q4,
           DATA    => Data_bus);
	end generate;
 
Prg_Memory_Controller : Program_Memory_Controller
Port map ( Prg_addr			=> Prg_addr,
			  Instruction		=> Inst_bus,
 
			  eff_Prg_addr		=> eff_Prg_addr,
			  Prg_memory_bus	=> Prg_memory_bus);
 
Prg_Memory : Program_Memory
Port map ( Address => eff_Prg_addr,
           nreset  => mcu_nreset,
           Q1      => Q1,
           Instruction => Prg_memory_bus);
 
 
--CLOCKpros : process(clk, nreset)
--begin
--	if nreset = '0' then
--		clk_2 <= '0';
--	elsif clk'event and clk = '1' then
--		clk_2 <= not clk_2;
--	end if;
--end process;
 
 
 
end Behavioral;