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-- Company:        Ferhat Abbas University - Algeria
-- Engineer:       Ibrahim MEZZAH
-- Progect Supervisor: Dr H. Chemali
-- Create Date:    14:43:38 05/24/05
-- Design Name:    Hard multiplier
-- Module Name:    Multiplier - Multiply
-- Project Name:   Microcontroller IP (MCIP)
-- Target Device:  xc3s500e-4fg320
-- Tool versions:  Xilinx ISE 9.1.03i
-- Description:	 This is a 8x8 multiplier.
-- Revision: 		 07/07/2008
-- Revision  1
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity Multiplier is
    Port ( Q          : in std_logic;
           MUL_enable : in std_logic;
           a          : in std_logic_vector(7 downto 0);
           b          : in std_logic_vector(7 downto 0);
			  PROD       : out std_logic_vector(15 downto 0));
end Multiplier;
 
architecture Multiply of Multiplier is
 
begin
 
	process(Q, a, b)
	  begin
		  if (rising_edge(Q) and MUL_enable = '1') then
			  PROD <= a*b;
		  end if;
	  end process;
 
end Multiply;