Subversion Repositories mcip_open

--------------------------------------------------------------------------------
-- Company:        Ferhat Abbas University - Algeria
-- Engineer:       Ibrahim MEZZAH
-- Progect Supervisor: Dr H. Chemali
-- Create Date:    23:44:46 05/28/05
-- Design Name:    Process unit
-- Module Name:    Calcul_Unit - Calcul
-- Project Name:   Microcontroller IP (MCIP)
-- Target Device:  xc3s500e-4fg320
-- Tool versions:  Xilinx ISE 9.1.03i
-- Description:	 This process unit includes 8-bits ALU,
--						 hard multiplier, and several 8-bits work registers
--						 WREG, WREGs, PRODL, PRODH, FREG.
-- Revision: 		 07/07/2008
-- Revision  2.2 - Add description
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity Operation_Unit is
    Port ( nreset        : in std_logic;
           Q             : in std_logic_vector(1 to 4);
			  CommandVector : in std_logic_vector(13 downto 0);
           CommandStatus : in std_logic_vector(4 downto 0);
           OldStatus     : in std_logic_vector(4 downto 0);
           R_W           : in std_logic_vector(1 downto 0);
           BitOp         : in std_logic_vector(2 downto 0);
			  call_return   : in std_logic_vector(1 downto 0);
			  Address_Latch : in std_logic_vector(1 downto 0);
			  BitOp_enable  : in std_logic;
			  WREG_write    : in std_logic;
			  MUL_enable    : in std_logic;
			  Read_result   : in std_logic;
			  Load_FREG     : in std_logic;
           DATA          : inout std_logic_vector(7 downto 0);
           NewStatus     : out std_logic_vector(4 downto 0);
			  SetResponse   : out std_logic_vector(1 downto 0) ); 
end Operation_Unit;
 
architecture Behavioral of Operation_Unit is
 
component ALU
    Port ( CommandVector : in std_logic_vector(13 downto 0);
			  CommandStatus : in std_logic_vector(4 downto 0);
			  OldStatus     : in std_logic_vector(4 downto 0);
			  a             : in std_logic_vector(7 downto 0);
			  b             : in std_logic_vector(7 downto 0);
			  s             : out std_logic_vector(7 downto 0);
			  NewStatus     : out std_logic_vector(4 downto 0);
			  SetResponse   : out std_logic_vector(1 downto 0) );
end component ALU;
 
component Multiplier
    Port ( Q          : in std_logic;
			  MUL_enable : in std_logic;
			  a          : in std_logic_vector(7 downto 0);
			  b          : in std_logic_vector(7 downto 0);
			  PROD       : out std_logic_vector(15 downto 0) );
end component Multiplier;
 
	signal WREG  : std_logic_vector(7 downto 0);
	signal PRODL : std_logic_vector(7 downto 0);
	signal PRODH : std_logic_vector(7 downto 0);
	signal FREG  : std_logic_vector(7 downto 0);
	signal WREGs : std_logic_vector(7 downto 0);
 
	signal DATA_read  : std_logic_vector(7 downto 0);
	signal DATA_write : std_logic_vector(7 downto 0);
 
	signal a_ALU  : std_logic_vector(7 downto 0);
	signal b_ALU  : std_logic_vector(7 downto 0);
	signal result : std_logic_vector(7 downto 0);
 
	signal PROD : std_logic_vector(15 downto 0);
 
   alias read_D  : std_logic is R_W(1);
   alias write_D : std_logic is R_W(0);
 
	alias Q1 : std_logic is Q(1);
	alias Q2 : std_logic is Q(2);
	alias Q3 : std_logic is Q(3);
	alias Q4 : std_logic is Q(4);
 
begin
 
ALUnit : ALU
port map (  CommandVector => CommandVector,
				CommandStatus => CommandStatus,
				OldStatus     => OldStatus,
				a             => a_alu,
				b             => b_alu,
				s             => result,
				NewStatus     => NewStatus,
				SetResponse   => SetResponse );
 
MUL : Multiplier
Port map ( Q          => Q3,
			  MUL_enable => MUL_enable,
			  a          => FREG,
			  b          => WREG,
			  PROD       => PROD );
 
	a_alu <= FREG;
	b_alu <= WREG(7 downto 3) & BitOp				 when BitOp_enable = '1' else
				WREG;
 
	DATA_read <= PRODL									 when Address_Latch(0) = '1' else
					 PRODH									 when Address_Latch(1) = '1' else
					 WREG;
 
	DATA_write <= DATA;
 
Latchs_p :  process (nreset, Q1, Q2, Q3, Q4, write_D, DATA_write, MUL_enable,
							call_return, Address_Latch, PROD, WREGs, WREG, Load_FREG)
  begin
		 if nreset = '0' then
				 WREG  <= (others => '0');
				 PRODH <= (others => '0');
				 PRODL <= (others => '0');
				 FREG  <= (others => '0');
				 WREGs <= (others => '0');
		 else
		  if (Q4'event and Q4 = '1') then
			if MUL_enable = '1' then
				PRODL <= PROD(7 downto 0);
				PRODH <= PROD(15 downto 8);
			else
				if write_D = '1' then
				 if Address_Latch(1) = '1' then
					 PRODH <= DATA_write;
				 elsif Address_Latch(0) = '1' then
					 PRODL <= DATA_write;
				 end if;
				end if;
			end if;
			if WREG_write = '1' or
				(write_D = '1' and Address_Latch = "00") then
				WREG <= DATA_write;
			elsif call_return(1) = '1' then
			 	if call_return(0) = '0' then
			  		WREGs <= WREG;						-- call
			 	else		
			  		WREG <= WREGs;						-- return
			 	end if; 										
			end if;
		  end if;
		  if ((Q2'event and Q2 = '1') and Load_FREG = '1') then 
			 FREG <= DATA_write;
		  end if;
		 end if;
	end process;
 
	 DATA <= DATA_read						when (Q1 = '1' and read_D = '1') else
				result							when (Q3 = '1' and Read_result = '1') else
				(others => 'Z');
 
end Behavioral;