Subversion Repositories mcip_open

--------------------------------------------------------------------------------
-- Company:        Ferhat Abbas University - Algeria
-- Engineer:       Ibrahim MEZZAH
-- Progect Supervisor: Dr H. Chemali
-- Create Date:    02:10:11 05/21/01
-- Design Name:    Phase Lock Loop
-- Module Name:    PLL - Behavioral
-- Project Name:   Microcontroller IP (MCIP)
-- Target Device:  xc3s500e-4fg320
-- Tool versions:  Xilinx ISE 9.1.03i
-- Description:    The PLL divide the clock input by four. It provides an
--                 instruction cycle that is the same frequency 
--                 as the external clock frequency. Four non-overlapping 
--                 quadrature clocks, namely Q1, Q2, Q3 and Q4 are generated.
-- Revision: 		 07/06/2008
-- Revision 3
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity PLL is
    Port ( clock             : in std_logic;
           nreset            : in std_logic;
           IDLEN				  : in std_logic;
           Sleep_mode_enable : in std_logic;
           Q1                : out std_logic;
           Q2                : out std_logic;
           Q3                : out std_logic;
           Q4                : out std_logic;
           internal_clock	  : out std_logic);  -- MCU clock/4
end PLL;
 
architecture Behavioral of PLL is
 
	signal Q : std_logic_vector(1 to 4);
	signal Syc : std_logic_vector(1 downto 0);
	signal Idle_Syc : std_logic;
	signal Idle : std_logic;
 
	signal clock_div4 : std_logic;
 
	signal nresetQ1 : std_logic;
	signal nresetQ3 : std_logic;
 
begin
 
	  nresetQ1 <= '0'						 when nreset = '0' or Q(2) = '1' else
					  '1';
	  nresetQ3 <= '0'						 when nreset = '0' or Q(4) = '1' else
					  '1';
	  Idle 	  <= '1'						 when Sleep_mode_enable = '1' and Idle_Syc = '1' else
					  '0';
 
	  Q1 <= Q(1);
	  Q2 <= Q(2);
	  Q3 <= Q(3);
	  Q4 <= Q(4);
 
	  internal_clock <= clock_div4;
 
	Sychronise : process(nreset, clock, Idle, IDLEN, Syc)
	begin
		if nreset = '0' then
			Syc <= "10";
		else
			if clock'event and clock = '1' then
				case Syc is
					when "10" =>
						if Idle = '1' and IDLEN = '0' then
							Syc <= "10";
						else
							Syc <= "00";
						end if;
					when "00" =>
						Syc <= "01";
					when "01" =>
						Syc <= "11";
					when others =>
						Syc <= "10";
				end case;
			else
				Syc <= Syc;
			end if;
		end if;
	end process;
 
	Out_clock : process(nreset, clock, Idle, IDLEN, Syc)
	begin
		if nreset = '0' then
			clock_div4 <= '0';
		else
			if clock'event and clock = '1' then
				case Syc is
					when "10" =>
						if Idle = '1' and IDLEN = '0' then
							clock_div4 <= clock_div4;
						else
							clock_div4 <= '0';
						end if;
					when "00" =>
						clock_div4 <= '0';
					when "01" =>
						clock_div4 <= '1';
					when others =>
						clock_div4 <= '1';
				end case;
			else
				clock_div4 <= clock_div4;
			end if;
		end if;
	end process;
 
	Q1_p : process(nresetQ1, clock, Idle, Syc)
	begin
		if nresetQ1 = '0' then
			Q(1) <= '0';
		else
			if clock'event and clock = '1' then
				if Syc = "10" then
					if Idle = '0' then
						Q(1) <= '1';
					else
						Q(1) <= Q(1);
					end if;
				else
					Q(1) <= Q(1);
				end if;
			else
				Q(1) <= Q(1);
			end if;
		end if;
	end process;
 
	Q2_p : process(nreset, clock, Idle_Syc, Syc)
	begin
		if nreset = '0' then
			Q(2) <= '0';
		else
			if clock'event and clock = '1' then
				if Syc = "00" then
					if Idle_Syc = '0' then
						Q(2) <= '1';
					else
						Q(2) <= '0';
					end if;
				else
					Q(2) <= '0';
				end if;
			else
				Q(2) <= Q(2);
			end if;
		end if;
	end process;
 
	Q3_p : process(nresetQ3, clock, Idle_Syc, Syc)
	begin
		if nresetQ3 = '0' then
			Q(3) <= '0';
		else
			if clock'event and clock = '1' then
				if Syc = "01" then
					if Idle_Syc = '0' then
						Q(3) <= '1';
					else
						Q(3) <= Q(3);
					end if;
				else
					Q(3) <= Q(3);
				end if;
			else
				Q(3) <= Q(3);
			end if;
		end if;
	end process;
 
	Q4_p : process(nreset, clock, Idle_Syc, Syc)
	begin
		if nreset = '0' then
			Q(4) <= '0';
		else
			if clock'event and clock = '1' then
				if Syc = "11" then
					if Idle_Syc = '0' then
						Q(4) <= '1';
					else
						Q(4) <= Q(4);
					end if;
				elsif Syc = "10" then
					if Idle = '0' then
						Q(4) <= '0';
					else
						Q(4) <= Q(4);
					end if;
				else
					Q(4) <= Q(4);
				end if;
			else
				Q(4) <= Q(4);
			end if;
		end if;
	end process;
 
	Idel_state : process(nreset, Q(1), Q(4), Sleep_mode_enable)
	begin
		if nreset = '0' or Q(1) = '1' then
			Idle_Syc <= '0';
		else
			if Q(4)'event and Q(4) = '1' then
				Idle_Syc <= Sleep_mode_enable;
			else
				Idle_Syc <= Idle_Syc;
			end if;
		end if;
	end process;
 
 
end Behavioral;