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[/] [mcip_open/] [trunk/] [MCIPopen_XilinxISEproject/] [PORTs.vhd] - Rev 4
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-------------------------------------------------------------------------------- -- Company: Ferhat Abbas University - Algeria -- Engineer: Ibrahim MEZZAH -- Progect Supervisor: Dr H. Chemali -- Create Date: 14:36:31 05/24/05 -- Design Name: In/Out Ports -- Module Name: Ports - InOutPorts -- Project Name: Microcontroller IP (MCIP) -- Target Device: xc3s500e-4fg320 -- Tool versions: Xilinx ISE 9.1.03i -- Description: Simple peripherals: 4 General purpose I/O configurable -- ports --> PORTA, PORTB, PORTC and PORTD. -- PORTB includes 3 External Interrupts: -- Revision: 07/06/2008 -- Revision 2 - Add description -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity PORTs is Port ( nreset : in std_logic; Q1 : in std_logic; Q4 : in std_logic; RE : in std_logic; WE : in std_logic; SFRs_Address : in std_logic_vector(3 downto 0); -- data_addr(4&3&1&0) DATA : inout std_logic_vector(7 downto 0); PORTA : inout std_logic_vector(7 downto 0); PORTB : inout std_logic_vector(7 downto 0); PORTC : inout std_logic_vector(7 downto 0); PORTD : inout std_logic_vector(7 downto 0)); end PORTs; architecture Behavioral of PORTs is signal data_read : std_logic_vector(7 downto 0); signal TRISA : std_logic_vector(7 downto 0); signal TRISB : std_logic_vector(7 downto 0); signal TRISC : std_logic_vector(7 downto 0); signal TRISD : std_logic_vector(7 downto 0); signal LATA : std_logic_vector(7 downto 0); signal LATB : std_logic_vector(7 downto 0); signal LATC : std_logic_vector(7 downto 0); signal LATD : std_logic_vector(7 downto 0); begin -- SFRs write operation --------------------------------- Write_pros : process( nreset, Q4, WE, SFRs_Address, DATA) begin if nreset = '0' then LATA <= (others => '0'); LATB <= (others => '0'); LATC <= (others => '0'); LATD <= (others => '0'); TRISA <= (others => '1'); TRISB <= (others => '1'); TRISC <= (others => '1'); TRISD <= (others => '1'); elsif Q4'event and Q4 = '1' then if WE = '1' then case SFRs_Address is -- SFR address when "1010" => TRISA <= DATA; -- F92 when "1011" => TRISB <= DATA; -- F93 when "1000" => TRISC <= DATA; -- F94 when "1001" => TRISD <= DATA; -- F95 when "0101" => LATA <= DATA; -- F89 when "0110" => LATB <= DATA; -- F8A when "0111" => LATC <= DATA; -- F8B when "0100" => LATD <= DATA; -- F8C when "0000" => LATA <= DATA; -- F80 when "0001" => LATB <= DATA; -- F81 when "0010" => LATC <= DATA; -- F82 when "0011" => LATD <= DATA; -- F83 when others => null; end case; end if; end if; end process; -- SFRs read operation ---------------------------------------------- data_read <= TRISA when SFRs_Address = "1010" else TRISB when SFRs_Address = "1011" else TRISC when SFRs_Address = "1000" else TRISD when SFRs_Address = "1001" else LATA when SFRs_Address = "0101" else LATB when SFRs_Address = "0110" else LATC when SFRs_Address = "0111" else LATD when SFRs_Address = "0100" else PORTA when SFRs_Address = "0000" else PORTB when SFRs_Address = "0001" else PORTC when SFRs_Address = "0010" else PORTD; --when SFRs_Address = "0011" DATA <= data_read when (Q1 = '1' and RE = '1') else (others => 'Z'); -- IO PORTs assignements --------------------------------- PORA : process(TRISA, LATA) begin for i in 0 to 7 loop if TRISA(i) = '0' then PORTA(i) <= LATA(i); else PORTA(i) <= 'Z'; end if; end loop; end process; PORB : process(TRISB, LATB) begin for i in 0 to 7 loop if TRISB(i) = '0' then PORTB(i) <= LATB(i); else PORTB(i) <= 'Z'; end if; end loop; end process; PORC : process(TRISC, LATC) begin for i in 0 to 7 loop if TRISC(i) = '0' then PORTC(i) <= LATC(i); else PORTC(i) <= 'Z'; end if; end loop; end process; PORD : process(TRISD, LATD) begin for i in 0 to 7 loop if TRISD(i) = '0' then PORTD(i) <= LATD(i); else PORTD(i) <= 'Z'; end if; end loop; end process; end Behavioral;