Subversion Repositories mcip_open

--------------------------------------------------------------------------------
-- Company:        Ferhat Abbas University - Algeria
-- Engineer:       Ibrahim MEZZAH
-- Progect Supervisor: Dr H. Chemali
-- Create Date:    02:42:20 06/06/05
-- Design Name:    32 levels Stack
-- Module Name:    Stack_ram - Behavioral
-- Project Name:   Microcontroller IP (MCIP)
-- Target Device:  xc3s500e-4fg320
-- Tool versions:  Xilinx ISE 9.1.03i
-- Description:	 This is a 32x21-bits Stack Ram.
-- Revision:		 07/06/2008
-- Revision 1 - Add description
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
 
entity Stack_ram is
    Generic ( STKPTR_length : integer := 5 );
	 Port ( Q            : in std_logic;
			  write_enable : in std_logic;
			  STKPTR       : in std_logic_vector(STKPTR_length-1 downto 0);
           Data_write   : in std_logic_vector(20 downto 1);
           Data_read    : out std_logic_vector(20 downto 1));
end Stack_ram;
 
architecture Behavioral of Stack_ram is
 
	constant Stack_stage : integer := 2**(STKPTR_length);
 
	type stack_ram is array (0 to Stack_stage-1) of std_logic_vector (20 downto 1);
	signal STACKram : stack_ram;
 
begin
 
 write_p : process(Q, write_enable)
  begin
	if Q'event and Q ='1' then
	  if write_enable = '1' then
		 STACKram( CONV_INTEGER(STKPTR) ) <= Data_write;
	  end if;
	end if;
  end process;
 
	  Data_read <= STACKram( CONV_INTEGER(STKPTR) );
 
end Behavioral;