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-------------------------------------------------------------------------------- -- Company: Ferhat Abbas University - Algeria -- Engineer: Ibrahim MEZZAH -- Progect Supervisor: Dr H. Chemali -- Create Date: 23:51:43 07/13/05 -- Design Name: ALU Slice -- Module Name: alu_slice - simple -- Project Name: Microcontroller IP (MCIP) -- Target Device: xc3s500e-4fg320 -- Tool versions: Xilinx ISE 9.1.03i -- Description: This module based on two 4-inputs LUTs g and p provides a -- carry propagation path (CarryIn, CarryOut). according to the -- value of configuration bits gi and pi, the slice carry out -- a specific operation op(a,b,Ci)=s and Co. -- Revision: 07/07/2008 -- Revision 1 - Add description -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity alu_slice is Port ( g : in std_logic_vector(3 downto 0); p : in std_logic_vector(3 downto 0); a : in std_logic; b : in std_logic; ci : in std_logic; s : out std_logic; co : out std_logic); end alu_slice; architecture simple of alu_slice is signal gi01 : std_logic; signal gi23 : std_logic; signal gi : std_logic; signal pi : std_logic; signal pi01 : std_logic; signal pi23 : std_logic; begin gi01 <= g(0) when (b='0') else g(1); gi23 <= g(2) when (b='0') else g(3); pi01 <= p(0) when (b='0') else p(1); pi23 <= p(2) when (b='0') else p(3); gi <= gi01 when (a='0') else gi23; pi <= pi01 when (a='0') else pi23; s <= gi xor ci; co <= pi or (gi and ci); end simple;