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[/] [mcip_open/] [trunk/] [tb_MCIPopen_LCD.vhd] - Rev 5
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-- MCIPopen TestBench LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY tb_MCIPopen_LCD IS END tb_MCIPopen_LCD; ARCHITECTURE behavior OF tb_MCIPopen_LCD IS SIGNAL reset : std_logic := '1'; SIGNAL clk50MHz : std_logic := '0'; SIGNAL direction : std_logic := '0'; SIGNAL PORTA : std_logic_vector(7 downto 0) := (others => '0'); SIGNAL clock_out : std_logic; SIGNAL PORTB : std_logic_vector(7 downto 0); SIGNAL PORTC : std_logic_vector(7 downto 0); SIGNAL PORTD : std_logic_vector(7 downto 0); constant clock_period : time := 20 ns; BEGIN -- Component Instantiation uut: entity work.LCDapp_MCIPopen Generic map( STKPTR_length => 5, STVREN => '1', WDTPS => "0100", WDTEN => '0', Banks_number => 3, dm_TOPaddr => x"2FF", IAlength => 12, pm_TOPaddr => '0'&x"03FFF" ) Port map ( reset => reset, clk50MHz => clk50MHz, direction => direction, clock_out => clock_out, PORTA => PORTA, PORTB => PORTB, PORTC => PORTC, PORTD => PORTD); clock_process :process begin clk50MHz <= '0'; wait for clock_period/2; clk50MHz <= '1'; wait for clock_period/2; end process; -- Test Bench Statements tb : PROCESS BEGIN wait for 100 ns; -- wait until global set/reset completes reset <= '0'; wait; -- will wait forever END PROCESS tb; -- End Test Bench END;
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