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Subversion Repositories mem_ctrl

[/] [mem_ctrl/] [trunk/] [bench/] [verilog/] [sram_models/] [IDT71T67802/] [readme_71T67802] - Rev 29

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IDT71V2578 - s133/150/166/183/200 verilog models/testbench
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07/09/99
rev01 -   devoloped from IDT71V2576_rev01

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03/23/00
built from 71V2578 verilog file
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