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[/] [mem_ctrl/] [trunk/] [rtl/] [verilog/] [mc_dp.v] - Rev 4
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///////////////////////////////////////////////////////////////////// //// //// //// WISHBONE Memory Controller //// //// Data Path Module //// //// //// //// //// //// Author: Rudolf Usselmann //// //// rudi@asics.ws //// //// //// //// //// //// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ //// //// //// ///////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Rudolf Usselmann //// //// rudi@asics.ws //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer.//// //// //// //// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// //// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// //// POSSIBILITY OF SUCH DAMAGE. //// //// //// ///////////////////////////////////////////////////////////////////// // CVS Log // // $Id: mc_dp.v,v 1.1 2001-07-29 07:34:41 rudi Exp $ // // $Date: 2001-07-29 07:34:41 $ // $Revision: 1.1 $ // $Author: rudi $ // $Locker: $ // $State: Exp $ // // Change History: // $Log: not supported by cvs2svn $ // Revision 1.2 2001/06/03 11:37:17 rudi // // // 1) Fixed Chip Select Mask Register // - Power On Value is now all ones // - Comparison Logic is now correct // // 2) All resets are now asynchronous // // 3) Converted Power On Delay to an configurable item // // 4) Added reset to Chip Select Output Registers // // 5) Forcing all outputs to Hi-Z state during reset // // Revision 1.1.1.1 2001/05/13 09:39:47 rudi // Created Directory Structure // // // // `include "mc_defines.v" module mc_dp( clk, rst, csc, wb_cyc_i, mem_wb_ack_o, wb_data_i, wb_data_o, wb_read_go, mc_data_i, mc_dp_i, mc_data_o, mc_dp_o, dv, pack_le0, pack_le1, pack_le2, byte_en, par_err ); input clk, rst; input [31:0] csc; input wb_cyc_i; input mem_wb_ack_o; input [31:0] wb_data_i; output [31:0] wb_data_o; input wb_read_go; input [31:0] mc_data_i; input [3:0] mc_dp_i; output [31:0] mc_data_o; output [3:0] mc_dp_o; input dv; input pack_le0, pack_le1, pack_le2; // Pack Latch Enable input [3:0] byte_en; // High Active byte enables output par_err; //////////////////////////////////////////////////////////////////// // // Local Registers & Wires // reg [31:0] wb_data_o; reg [31:0] mc_data_o; wire [35:0] rd_fifo_out; reg [35:0] mc_data_del; wire rd_fifo_clr; reg [3:0] mc_dp_o; reg par_err_r; reg [7:0] byte0, byte1, byte2; reg [31:0] mc_data_d; wire [2:0] mem_type; wire [1:0] bus_width; wire pen; wire re; // Aliases assign mem_type = csc[3:1]; assign bus_width = csc[5:4]; assign pen = csc[11]; //////////////////////////////////////////////////////////////////// // // WB READ Data Path // always @(posedge clk) if(mem_type == `MEM_TYPE_SDRAM) wb_data_o <= #1 rd_fifo_out[31:0]; else if(mem_type == `MEM_TYPE_SRAM) wb_data_o <= #1 rd_fifo_out[31:0]; else wb_data_o <= #1 mc_data_d; always @(posedge clk) mc_data_del <= #1 {mc_dp_i, mc_data_i}; assign rd_fifo_clr = rst & wb_cyc_i; assign re = mem_wb_ack_o & wb_read_go; mc_rd_fifo u0( .clk( clk ), .rst( rd_fifo_clr ), .din( mc_data_del ), .we( dv ), .dout( rd_fifo_out ), .re( re ) ); //////////////////////////////////////////////////////////////////// // // WB WRITE Data Path // always @(posedge clk) if(mem_wb_ack_o | (mem_type != `MEM_TYPE_SDRAM) ) mc_data_o <= #1 wb_data_i; //////////////////////////////////////////////////////////////////// // // Read Data Packing // always @(posedge clk) if(pack_le0) byte0 <= #1 mc_data_i[7:0]; always @(posedge clk) if(pack_le1 & (bus_width == `BW_8)) byte1 <= #1 mc_data_i[7:0]; else if(pack_le0 & (bus_width == `BW_16)) byte1 <= #1 mc_data_i[15:8]; always @(posedge clk) if(pack_le2) byte2 <= #1 mc_data_i[7:0]; always @(bus_width or mc_data_i or byte0 or byte1 or byte2) if(bus_width == `BW_8) mc_data_d = {mc_data_i[7:0], byte2, byte1, byte0}; else if(bus_width == `BW_16) mc_data_d = {mc_data_i[15:0], byte1, byte0}; else mc_data_d = mc_data_i; //////////////////////////////////////////////////////////////////// // // Parity Generation // always @(posedge clk) if(mem_wb_ack_o | (mem_type != `MEM_TYPE_SDRAM) ) mc_dp_o <= #1 { ^wb_data_i[31:24], ^wb_data_i[23:16], ^wb_data_i[15:08], ^wb_data_i[07:00] }; //////////////////////////////////////////////////////////////////// // // Parity Checking // assign par_err = par_err_r & mem_wb_ack_o; always @(posedge clk) par_err_r <= #1 pen & ( (( ^rd_fifo_out[31:24] ^ rd_fifo_out[35] ) & byte_en[3] ) | (( ^rd_fifo_out[23:16] ^ rd_fifo_out[34] ) & byte_en[2] ) | (( ^rd_fifo_out[15:08] ^ rd_fifo_out[33] ) & byte_en[1] ) | (( ^rd_fifo_out[07:00] ^ rd_fifo_out[32] ) & byte_en[0] ) ); endmodule
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