Subversion Repositories mem_ctrl

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# Design Specification
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# Author: Rudolf Usselmann
#         rudi@asics.ws
#
# Revision:
# 3/7/01 RU Initial Sript
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#
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# ==============================================
# Setup Design Parameters

set design_files {mc_incn_r mc_mem_if mc_rd_fifo mc_timing mc_adr_sel mc_dp mc_obct mc_refresh mc_cs_rf mc_wb_if mc_obct_top mc_rf mc_top}

set design_name mc_top
set active_design mc_top
 
# Next Statement defines all clocks and resets in the design
set special_net {rst clk mc_clk}
 
set hdl_src_dir ../../rtl/verilog/