Subversion Repositories mesi_isc

{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1 1356436450049 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition " "Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1 1356436450050 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 25 13:54:09 2012 " "Processing started: Tue Dec 25 13:54:09 2012" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1356436450050 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1356436450050 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off mesi_isc -c mesi_isc " "Command: quartus_map --read_settings_files=on --write_settings_files=off mesi_isc -c mesi_isc" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1356436450050 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "" 0 -1 1356436450262 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_define.v 0 0 " "Found 0 design units, including 0 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_define.v" {  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1356436450369 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad_cntl.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad_cntl.v" { { "Info" "ISGN_ENTITY_NAME" "1 mesi_isc_broad_cntl " "Found entity 1: mesi_isc_broad_cntl" {  } { { "../src/rtl/mesi_isc_broad_cntl.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad_cntl.v" 47 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1356436450374 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1356436450374 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad.v" { { "Info" "ISGN_ENTITY_NAME" "1 mesi_isc_broad " "Found entity 1: mesi_isc_broad" {  } { { "../src/rtl/mesi_isc_broad.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad.v" 47 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1356436450376 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1356436450376 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "mesi_isc_breq_fifos_cntl.v(294) " "Verilog HDL information at mesi_isc_breq_fifos_cntl.v(294): always construct contains both blocking and non-blocking assignments" {  } { { "../src/rtl/mesi_isc_breq_fifos_cntl.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos_cntl.v" 294 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "" 0 -1 1356436450378 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos_cntl.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos_cntl.v" { { "Info" "ISGN_ENTITY_NAME" "1 mesi_isc_breq_fifos_cntl " "Found entity 1: mesi_isc_breq_fifos_cntl" {  } { { "../src/rtl/mesi_isc_breq_fifos_cntl.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos_cntl.v" 49 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1356436450379 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1356436450379 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos.v" { { "Info" "ISGN_ENTITY_NAME" "1 mesi_isc_breq_fifos " "Found entity 1: mesi_isc_breq_fifos" {  } { { "../src/rtl/mesi_isc_breq_fifos.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos.v" 67 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1356436450381 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1356436450381 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 mesi_isc_basic_fifo " "Found entity 1: mesi_isc_basic_fifo" {  } { { "../src/rtl/mesi_isc_basic_fifo.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v" 48 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1356436450383 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1356436450383 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" { { "Info" "ISGN_ENTITY_NAME" "1 mesi_isc " "Found entity 1: mesi_isc" {  } { { "../src/rtl/mesi_isc.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 47 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1356436450385 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1356436450385 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "mesi_isc " "Elaborating entity \"mesi_isc\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1 1356436450490 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mesi_isc_broad mesi_isc_broad:mesi_isc_broad " "Elaborating entity \"mesi_isc_broad\" for hierarchy \"mesi_isc_broad:mesi_isc_broad\"" {  } { { "../src/rtl/mesi_isc.v" "mesi_isc_broad" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 163 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1356436450495 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mesi_isc_broad_cntl mesi_isc_broad:mesi_isc_broad\|mesi_isc_broad_cntl:mesi_isc_broad_cntl " "Elaborating entity \"mesi_isc_broad_cntl\" for hierarchy \"mesi_isc_broad:mesi_isc_broad\|mesi_isc_broad_cntl:mesi_isc_broad_cntl\"" {  } { { "../src/rtl/mesi_isc_broad.v" "mesi_isc_broad_cntl" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad.v" 138 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1356436450497 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mesi_isc_basic_fifo mesi_isc_broad:mesi_isc_broad\|mesi_isc_basic_fifo:broad_fifo " "Elaborating entity \"mesi_isc_basic_fifo\" for hierarchy \"mesi_isc_broad:mesi_isc_broad\|mesi_isc_basic_fifo:broad_fifo\"" {  } { { "../src/rtl/mesi_isc_broad.v" "broad_fifo" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_broad.v" 170 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1356436450500 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 mesi_isc_basic_fifo.v(122) " "Verilog HDL assignment warning at mesi_isc_basic_fifo.v(122): truncated value with size 32 to match size of target (2)" {  } { { "../src/rtl/mesi_isc_basic_fifo.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v" 122 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1 1356436450504 "|mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "i mesi_isc_basic_fifo.v(112) " "Verilog HDL Always Construct warning at mesi_isc_basic_fifo.v(112): inferring latch(es) for variable \"i\", which holds its previous value in one or more paths through the always construct" {  } { { "../src/rtl/mesi_isc_basic_fifo.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v" 112 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 -1 1356436450504 "|mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 mesi_isc_basic_fifo.v(154) " "Verilog HDL assignment warning at mesi_isc_basic_fifo.v(154): truncated value with size 32 to match size of target (2)" {  } { { "../src/rtl/mesi_isc_basic_fifo.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v" 154 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1 1356436450504 "|mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 mesi_isc_basic_fifo.v(157) " "Verilog HDL assignment warning at mesi_isc_basic_fifo.v(157): truncated value with size 32 to match size of target (2)" {  } { { "../src/rtl/mesi_isc_basic_fifo.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v" 157 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1 1356436450504 "|mesi_isc|mesi_isc_broad:mesi_isc_broad|mesi_isc_basic_fifo:broad_fifo"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mesi_isc_breq_fifos mesi_isc_breq_fifos:mesi_isc_breq_fifos " "Elaborating entity \"mesi_isc_breq_fifos\" for hierarchy \"mesi_isc_breq_fifos:mesi_isc_breq_fifos\"" {  } { { "../src/rtl/mesi_isc.v" "mesi_isc_breq_fifos" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc.v" 200 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1356436450505 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mesi_isc_breq_fifos_cntl mesi_isc_breq_fifos:mesi_isc_breq_fifos\|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl " "Elaborating entity \"mesi_isc_breq_fifos_cntl\" for hierarchy \"mesi_isc_breq_fifos:mesi_isc_breq_fifos\|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl\"" {  } { { "../src/rtl/mesi_isc_breq_fifos.v" "mesi_isc_breq_fifos_cntl" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos.v" 174 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1356436450509 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 mesi_isc_breq_fifos_cntl.v(371) " "Verilog HDL assignment warning at mesi_isc_breq_fifos_cntl.v(371): truncated value with size 32 to match size of target (3)" {  } { { "../src/rtl/mesi_isc_breq_fifos_cntl.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos_cntl.v" 371 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1 1356436450512 "|mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_breq_fifos_cntl:mesi_isc_breq_fifos_cntl"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mesi_isc_basic_fifo mesi_isc_breq_fifos:mesi_isc_breq_fifos\|mesi_isc_basic_fifo:fifo_3 " "Elaborating entity \"mesi_isc_basic_fifo\" for hierarchy \"mesi_isc_breq_fifos:mesi_isc_breq_fifos\|mesi_isc_basic_fifo:fifo_3\"" {  } { { "../src/rtl/mesi_isc_breq_fifos.v" "fifo_3" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos.v" 234 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1356436450513 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 mesi_isc_basic_fifo.v(122) " "Verilog HDL assignment warning at mesi_isc_basic_fifo.v(122): truncated value with size 32 to match size of target (1)" {  } { { "../src/rtl/mesi_isc_basic_fifo.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v" 122 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1 1356436450515 "|mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "i mesi_isc_basic_fifo.v(112) " "Verilog HDL Always Construct warning at mesi_isc_basic_fifo.v(112): inferring latch(es) for variable \"i\", which holds its previous value in one or more paths through the always construct" {  } { { "../src/rtl/mesi_isc_basic_fifo.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v" 112 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 -1 1356436450515 "|mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 mesi_isc_basic_fifo.v(154) " "Verilog HDL assignment warning at mesi_isc_basic_fifo.v(154): truncated value with size 32 to match size of target (1)" {  } { { "../src/rtl/mesi_isc_basic_fifo.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v" 154 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1 1356436450515 "|mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 mesi_isc_basic_fifo.v(157) " "Verilog HDL assignment warning at mesi_isc_basic_fifo.v(157): truncated value with size 32 to match size of target (1)" {  } { { "../src/rtl/mesi_isc_basic_fifo.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v" 157 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1 1356436450516 "|mesi_isc|mesi_isc_breq_fifos:mesi_isc_breq_fifos|mesi_isc_basic_fifo:fifo_3"}
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "" 0 -1 1356436451844 ""}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "../src/rtl/mesi_isc_breq_fifos_cntl.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_breq_fifos_cntl.v" 177 -1 0 } } { "../src/rtl/mesi_isc_basic_fifo.v" "" { Text "/home/yair/Work/Projects/mesi_isc/src/rtl/mesi_isc_basic_fifo.v" 171 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "" 0 -1 1356436451905 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 -1 1356436451906 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "" 0 -1 1356436452498 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/yair/Work/Projects/mesi_isc/syn/mesi_isc.map.smsg " "Generated suppressed messages file /home/yair/Work/Projects/mesi_isc/syn/mesi_isc.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1 1356436453653 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "" 0 -1 1356436453827 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "" 0 -1 1356436453827 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "1101 " "Implemented 1101 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "146 " "Implemented 146 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "" 0 -1 1356436453981 ""} { "Info" "ICUT_CUT_TM_OPINS" "48 " "Implemented 48 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "" 0 -1 1356436453981 ""} { "Info" "ICUT_CUT_TM_LCELLS" "907 " "Implemented 907 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "" 0 -1 1356436453981 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1 1356436453981 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "370 " "Peak virtual memory: 370 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1356436453997 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 25 13:54:13 2012 " "Processing ended: Tue Dec 25 13:54:13 2012" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1356436453997 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1356436453997 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1356436453997 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1356436453997 ""}