Subversion Repositories mesi_isc

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#
# Copyright (C) 1991-2012 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
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# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 12.0 Build 263 08/02/2012 Service Pack 2 SJ Web Edition
# Date created = 09:58:58  November 06, 2012
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#               mesi_isc_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#               assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone IV GX"
set_global_assignment -name DEVICE auto
set_global_assignment -name TOP_LEVEL_ENTITY mesi_isc
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.0 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:58:58  NOVEMBER 06, 2012"
set_global_assignment -name LAST_QUARTUS_VERSION "12.0 SP2"
set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc_define.v
set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc_broad_cntl.v
set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc_broad.v
set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc_breq_fifos_cntl.v
set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc_breq_fifos.v
set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc_basic_fifo.v
set_global_assignment -name VERILOG_FILE ../src/rtl/mesi_isc.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top