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[/] [mini_aes/] [trunk/] [README] - Rev 17

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# $Id: README,v 1.1.1.1 2005-12-06 02:47:45 arif_endro Exp $

Directory Layout

.
|-- bench  -> the test bench directory
| 
|-- data   -> data files, `ecb_tbl.txt' file used for verification.
|
|-- doc    -> documentation files
|
`-- source -> the VHDL source of this project.

Test Bench

If you want to run the test bench, then go to the bench subdirectory and
then run the modelsim do file, i.e. `modelsim_bench.do'. This simulation
will generate an output into a file called `ecb_tbl_result_enc.txt' and
`ecb_tbl_result_dec.txt', then you can analyze those file to see the
result.

Sincerely,

Arif E. Nugroho
<arif_endro@yahoo.com>

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