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[/] [minimips_superscalar/] [tags/] [P1/] [sources/] [banc.vhd] - Rev 29
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-------------------------------------------------------------------------- -- -- -- -- -- miniMIPS Superscalar Processor : Register bank -- -- based on miniMIPS Processor -- -- -- -- -- -- Author : Miguel Cafruni -- -- miguel_cafruni@hotmail.com -- -- March 2020 -- -------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.pack_mips.all; entity banc is port ( clock : in bus1; clock2 : in bus1; reset : in bus1; -- Register addresses to read reg_src1 : in bus5; reg_src2 : in bus5; -- Register address to write and its data reg_dest : in bus5; donnee : in bus32; -- Write signal cmd_ecr : in bus1; -- Bank outputs data_src1 : out bus32; data_src2 : out bus32; -- Register addresses to read reg_src3 : in bus5; reg_src4 : in bus5; -- Register address to write and its data reg_dest2 : in bus5; donnee2 : in bus32; -- Write signal cmd_ecr2 : in bus1; -- Bank outputs data_src3 : out bus32; data_src4 : out bus32 ); end banc; architecture rtl of banc is -- The register bank type tab_reg is array (1 to 31) of std_logic_vector(31 downto 0); signal registres : tab_reg; signal adr_src1 : integer range 0 to 31; signal adr_src2 : integer range 0 to 31; signal adr_dest : integer range 0 to 31; signal adr_src3 : integer range 0 to 31; signal adr_src4 : integer range 0 to 31; signal adr_dest2 : integer range 0 to 31; signal clk, cmd1, cmd2 : bus1; begin -- _ _ _ _ clk <= clock or clock2; -- __| |________ or ______| |________ = ___| |___| |___ -- __________ _ _ cmd1 <= cmd_ecr and clock; -- ___| |_________ X __| |________ = __| |________ -- __________ _ _ cmd2 <= cmd_ecr2 and clock2;-- ______________| |__ X _____| |________ = _____| |________ adr_src1 <= to_integer(unsigned(reg_src1)); adr_src2 <= to_integer(unsigned(reg_src2)); adr_dest <= to_integer(unsigned(reg_dest)); adr_src3 <= to_integer(unsigned(reg_src3)); adr_src4 <= to_integer(unsigned(reg_src4)); adr_dest2 <= to_integer(unsigned(reg_dest2)); data_src1 <= (others => '0') when adr_src1=0 else registres(adr_src1); data_src2 <= (others => '0') when adr_src2=0 else registres(adr_src2); data_src3 <= (others => '0') when adr_src3=0 else registres(adr_src3); data_src4 <= (others => '0') when adr_src4=0 else registres(adr_src4); process(clk, cmd1, cmd2) begin if rising_edge(clk) then if reset='1' then for i in 1 to 31 loop registres(i) <= (others => '0'); end loop; elsif cmd1 = '1' and adr_dest /= 0 then -- The data is saved registres(adr_dest) <= donnee; else if cmd2 = '1' and adr_dest2 /= 0 then -- The data is saved registres(adr_dest2) <= donnee2; end if; end if; end if; end process; end rtl;