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Subversion Repositories minimips_superscalar

[/] [minimips_superscalar/] [trunk/] [gasm_with_mult2_instruction/] [Syntaxe] - Rev 22

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; This file is part of gasm.
;
;    
; If you encountered any problem, please contact :
;                                                 
;   lmouton@enserg.fr                             
;   shangoue@enserg.fr                            
;                                                 



;===============================================================================;
;                                                                               ;
;                                                                               ;
; Fichier de donnees sur la syntaxe de l'assembleur du microprocesseur miniMIPS ;
;                                                                               ;
;                                                                               ;
;===============================================================================;




SET UNDEFSTR    U                       ; Chaine de supression de macro

; d'assemblage sera interdite...
; SET INCLUDESTR        I               ; Chaine d'inclusion de fichier

SET SEP


SET NEWSST      Reg     $?09    1
SET NEWSST      Reg     $?02?09 1
SET NEWSST      Reg     $3?01   1


; Autorise les lignes vides
{
}

{ Alpha: }


{ Alpha EQU Alpha }
        FUN     AddEqu

{ Alpha EQU Int }
        FUN     AddEqu

{ ALIGN4 }
        FUN     Complete_zeros

{ DCB Int }
        TMO     1
        MSK     _0000_0000_
        FUN     Dcb_Int
{ DCB Alpha }
        TMO     1
        MSK     _0000_0000_
        FUN     Dcb_Alpha
{ DCW Int }
        TMO     4
        MSK     _0000_0000_0000_0000__0000_0000_0000_0000_
        FUN     Dcw_Int
{ DCW Alpha }
        TMO     2
        MSK     _0000_0000_0000_0000__0000_0000_0000_0000_
        FUN     Dcw_Alpha

; Directives de positionnement de l'adresse d'implantation
{ ORG Int }
        FUN     Org_Int

{ ORG Alpha }
        FUN     Org_Label

; DEFINITION DES INSTRUCTIONS

; Instruction ADD
{ ADD Reg, Reg, Reg }
        TMO     4
        MSK     _000000_00000_00000_00000_00000_100000
        FUN     R1D
        FUN     R3S
        FUN     R5T

; Instruction ADDI
{ ADDI Reg, Reg, Int }
    TMO     4
    MSK _001000_00000_00000__00000000_00000000
    FUN     R1T
    FUN     R3S
    FUN     IMM5
{ ADDI Reg, Reg, Alpha }
    TMO     4
    MSK _001000_00000_00000__00000000_00000000
    FUN     R1T
    FUN     R3S
    FUN     ETIQ5

; Instruction ADDIU
{ ADDIU Reg, Reg, Int }
    TMO     4
    MSK _001001_00000_00000__00000000_00000000
    FUN     R1T
    FUN     R3S
    FUN     IMM5

; Instruction ADDU
{ ADDU Reg, Reg, Reg }
        TMO     4
        MSK     _000000_00000_00000_00000_00000_100001
        FUN     R1D
        FUN     R3S
        FUN     R5T

; Instruction AND
{ AND Reg, Reg, Reg }
        TMO     4
        MSK     _000000_00000_00000_00000_00000_100100
        FUN     R1D
        FUN     R3S
        FUN     R5T

; Instruction ANDI
{ ANDI Reg, Reg, Int }
        TMO     4
        MSK     _001100_00000_00000__00000000_00000000
        FUN     R1T
        FUN     R3S
        FUN     IMM5
{ ANDI Reg, Reg, Alpha }
        TMO     4
        MSK     _001100_00000_00000__00000000_00000000
        FUN     R1T
        FUN     R3S
        FUN     ETIQ5

; Instruction BEQ
{ BEQ Reg, Reg, Alpha }
        TMO     4
        MSK     _000100_00000_00000__0000_0000_0000_0000
        FUN     R1S
        FUN     R3T
        FUN     OFFSET5

; Instruction BGEZ
{ BGEZ Reg, Alpha }
        TMO     4
        MSK     _000001_00000_00001__00000000_00000000
        FUN     R1S
        FUN     OFFSET3

; Instruction BGEZAL
{ BGEZAL Reg, Alpha }
        TMO     4
        MSK     _000001_00000_10001__00000000_00000000
        FUN     R1S
        FUN     OFFSET3

; Instruction BGTZ
{ BGTZ Reg, Alpha }
        TMO     4
        MSK     _000111_00000_00000__00000000_00000000
        FUN     R1S
        FUN     OFFSET3

; Instruction BLEZ
{ BLEZ Reg, Alpha }
        TMO     4
        MSK     _000110_00000_00000__00000000_00000000
        FUN     R1S
        FUN     OFFSET3

; Instruction BLTZ
{ BLTZ Reg, Alpha }
        TMO     4
        MSK     _000001_00000_00000__00000000_00000000
        FUN     R1S
        FUN     OFFSET3

; Instruction BLTZAL
{ BLTZAL Reg, Alpha }
        TMO     4
        MSK     _000001_00000_10000__00000000_00000000
        FUN     R1S
        FUN     OFFSET3

; Instruction BNE
{ BNE Reg, Reg, Alpha }
        TMO     4
        MSK     _000101_00000_00000__00000000_00000000
        FUN     R1S
        FUN     R3T
        FUN     OFFSET5

; Instruction BREAK
{ BREAK }
        TMO     4
        MSK     _000000__00000_00000_00000_00000__001101

; Instruction COP0
{ COP0 Int }
        TMO     4
        MSK     _010000_00001_00000_0000_0000_0000_0000
    FUN IMM1

; Instruction J
{ J Alpha }
        TMO     4
        MSK     _000010__00_0000_0000_0000_0000_0000_0000
        FUN     ABSOLU1

; Instruction JAL
{ JAL Alpha }
        TMO     4
        MSK     _000011__00_0000_0000_0000_0000_0000_0000
        FUN     ABSOLU1

; Instruction JALR
{ JAL Reg, Reg }
        TMO     4
        MSK     _000000_00000_00000_00000_00000_001001
        FUN     R1D
        FUN     R3S

; Instruction JALR avec rd=$31 implicite
{ JAL Reg }
        TMO     4
        MSK     _000000_00000_00000_11111_00000_001001
        FUN     R1S

; Instruction JR
{ JR Reg }
        TMO     4
        MSK     _000000_00000__000_0000_0000_0000__001000
        FUN     R1S

; Instruction LUI
{ LUI Reg, Int }
    TMO 4
    MSK _001111_00000_00000__0000_0000_0000_0000
    FUN R1T
    FUN IMM3
{ LUI Reg, Alpha }
    TMO 4
    MSK _001111_00000_00000__0000_0000_0000_0000
    FUN R1T
    FUN ETIQ3

; Instruction LW
{ LW Reg, Int(Reg) }
        TMO     4
        MSK     _100011_00000_00000__0000_0000_0000_0000
        FUN     R1T
        FUN     IMM3
        FUN     R5S

; Instruction LWC0
{ LWC0 Reg, Int(Reg) }
    TMO 4
    MSK _110000_00000_00000__0000_0000_0000_0000
    FUN R1T
    FUN IMM3
    FUN R5S

; Instruction MFC0
{ MFC0 Reg, Reg }
    TMO 4
    MSK _010000_00000_00000_00000__000000_00000
    FUN R1D
    FUN R3T

; Instruction MFHI
{ MFHI Reg }
        TMO     4
        MSK     _000000_0000000000_00000_00000_010000
        FUN     R1D

; Instruction MFLO
{ MFLO Reg }
        TMO     4
        MSK     _000000_0000000000_00000_00000_010010
        FUN     R1D

; Instruction MTC0
{ MTC0 Reg, Reg }
    TMO 4
    MSK _010000_00100_00000_00000__000000_00000
    FUN R1T
    FUN R3D

; Instruction MTHI
{ MTHI Reg }
        TMO     4
        MSK     _000000_00000__0_0000_0000_0000_00__010001
        FUN     R1S

; Instruction MTLO
{ MTLO Reg }
        TMO     4
        MSK     _000000_00000__0_0000_0000_0000_00__010011
        FUN     R1S

; Instruction MULT
{ MULT Reg, Reg }
    TMO 4
    MSK _000000_00000_00000__0000_0000_00__011000
    FUN R1S
    FUN R3T
; Instruction MULT2
{ MULT2 Reg, Reg, Reg }
        TMO     4
        MSK     _000000_00000_00000_00000_00000_011100
        FUN     R1D
        FUN     R3S
        FUN     R5T

; Instruction MULTU
{ MULTU Reg, Reg }
    TMO 4
    MSK _000000_00000_00000__0000_0000_00__011001
    FUN R1S
    FUN R3T

; Instruction NOR
{ NOR Reg, Reg, Reg }
        TMO     4
        MSK     _000000_00000_00000_00000_00000_100111
        FUN     R1D
        FUN     R3S
        FUN     R5T

; Instruction OR
{ OR Reg, Reg, Reg }
        TMO     4
        MSK     _000000_00000_00000_00000_00000_100101
        FUN     R1D
        FUN     R3S
        FUN     R5T

; Instruction ORI
{ ORI Reg, Reg, Int }
    TMO     4
        MSK     _001101_00000_00000__00000000_00000000
    FUN     R1T
    FUN     R3S
    FUN     IMM5
{ ORI Reg, Reg, Alpha }
    TMO     4
        MSK         _001101_00000_00000__00000000_00000000
    FUN     R1T
    FUN     R3S
    FUN     ETIQ5

; Instruction SLL
{ SLL Reg, Reg, Int }
        TMO     4
        MSK     _000000_00000_00000_00000_00000_000000
        FUN     R1D
        FUN     R3T
        FUN     SA5

; Instruction SLLV
{ SLLV Reg, Reg, Reg }
        TMO     4
        MSK     _000000_00000_00000_00000_00000_000100
        FUN     R1D
        FUN     R3T
        FUN     R5S

; Instruction SLT
{ SLT Reg, Reg, Reg }
        TMO     4
        MSK     _000000_00000_00000_00000_00000_101010
        FUN     R1D
        FUN     R3S
        FUN     R5T

; Instruction SLTI
{ SLTI Reg, Reg, Int }
    TMO     4
        MSK     _001010_00000_00000__00000000_00000000
    FUN     R1T
    FUN     R3S
    FUN     IMM5
{ SLTI Reg, Reg, Alpha }
    TMO     4
        MSK     _001010_00000_00000__00000000_00000000
    FUN     R1T
    FUN     R3S
    FUN     ETIQ5

; Instruction SLTIU
{ SLTIU Reg, Reg, Int }
    TMO     4
    MSK     _001010_00000_00000__00000000_00000000
    FUN     R1T
    FUN     R3S
    FUN     IMM5
{ SLTIU Reg, Reg, Alpha }
    TMO     4
    MSK     _001010_00000_00000__00000000_00000000
    FUN     R1T
    FUN     R3S
    FUN     ETIQ5

; Instruction SLTU
{ SLTU Reg, Reg, Reg }
        TMO     4
        MSK     _000000_00000_00000_00000_00000_101011
        FUN     R1D
        FUN     R3S
        FUN     R5T

; Instruction SRA
{ SRA Reg, Reg, Int }
        TMO     4
        MSK     _000000_00000_00000_00000_00000_000011
        FUN     R1D
        FUN     R3T
        FUN     SA5

; Instruction SRAV
{ SRAV Reg, Reg, Reg }
        TMO     4
        MSK     _000000_00000_00000_00000_00000_000111
        FUN     R1D
        FUN     R3T
        FUN     R5S

; Instruction SRL
{ SRL Reg, Reg, Int }
        TMO     4
        MSK     _000000_00000_00000_00000_00000_000010
        FUN     R1D
        FUN     R3T
        FUN     SA5

; Instruction SRLV
{ SRLV Reg, Reg, Reg }
        TMO     4
        MSK     _000000_00000_00000_00000_00000_000110
        FUN     R1D
        FUN     R3T
        FUN     R5S

; Instruction SUB
{ SUB Reg, Reg, Reg }
        TMO     4
        MSK     _000000_00000_00000_00000_00000_100010
        FUN     R1D
        FUN     R3S
        FUN     R5T

; Instruction SUBU
{ SUBU Reg, Reg, Reg }
        TMO     4
        MSK     _000000_00000_00000_00000_00000_100011
        FUN     R1D
        FUN     R3S
        FUN     R5T

; Instruction SW
{ SW Reg, Int(Reg) }
        TMO     4
        MSK     _101011_00000_00000__0000_0000_0000_0000
        FUN     R1T
        FUN     IMM3
        FUN     R5S

; Instruction SWC0
{ SWC0 Reg, Int(Reg) }
        TMO     4
        MSK     _111000_00000_00000__0000_0000_0000_0000
        FUN     R1T
        FUN     IMM3
        FUN     R5S

; Instruction SYSCALL
{ SYSCALL }
        TMO     4
        MSK     _000000__00000_00000_00000_00000__001100

; Instruction XOR
{ XOR Reg, Reg, Reg }
        TMO     4
        MSK     _000000_00000_00000_00000_00000_100110
        FUN     R1D
        FUN     R3S
        FUN     R5T

; Instruction XORI
{ XORI Reg, Reg, Int }
    TMO     4
        MSK     _001110_00000_00000__00000000_00000000
    FUN     R1T
    FUN     R3S
    FUN     IMM5
{ XORI Reg, Reg, Alpha }
    TMO     4
        MSK     _001110_00000_00000__00000000_00000000
    FUN     R1T
    FUN     R3S
    FUN     ETIQ5

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