Subversion Repositories minirisc

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<p><b><font size=+2 face="Helvetica, Arial"
color=#bf0000>Project Name: Mini-Risc core</font></b> </p>
<p>(See change Log at bottom of page for changes/updates)</p>
<P> </P>
<p><font size="+1"><u>Description: </u></font></p>
<p>This is a Mini-RISC CPU/Microcontroller that is compatible with the PIC 16C57 
  from Microchip. Additional information about the instruction set and capabilities 
  can be found at: www.microchip.com</p>
<p>
</p>
<p><u><font size="+1">Legal Notice</font></u></p>
<p><font color="#FF0000">PIC, Microchip, etc. are Trademarks of Microchip Technology 
  Inc. I have no idea if implementing this core will or will not violate patents, 
  copyrights or cause any other type of lawsuits. I provide this core AS IS, without 
  any warranties. If you decide to build this core, you are responsible for any 
  legal resolutions, such as patents and copyrights, and perhaps others ....</font> 
  <font color="#FF0000">This source files may be used and distributed without</font> 
  <font color="#FF0000">restriction provided that all copyright statement are 
  not</font> <font color="#FF0000">removed from the files and that any derivative 
  work contains</font> <font color="#FF0000">the original copyright notices and 
  the associated disclaimer.</font></p>
<blockquote> 
  <blockquote> 
    <p><font face="Times"> <b><font color="#FF0000">THIS SOURCE FILES ARE PROVIDED 
      "AS IS" AND WITHOUT ANY</font></b></font><br>
      <font color="#FF0000"><b><font face="Times">EXPRESS OR IMPLIED WARRANTIES, 
      INCLUDING, WITHOUT<br>
      LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND</font></b></font><br>
      <font color="#FF0000"><b><font face="Times">FITNESS FOR A PARTICULAR PURPOSE.</font></b></font></p>
  </blockquote>
</blockquote>
<p> </p>
<p><font size="+1"><u>Motivation</u><u></u></font></p>
<ul>
  <li>A PIC compatible Microcontroller that runs a lot faster</li>
  <li>Synthesisable and technology independent design</li>
  <li>Separate (External to the core) Program Memory</li>
  <li>Options to extend the core<font face="Georgia, Times New Roman, Times, serif" size="+1"> 
    </font></li>
</ul>
<p><font size="+2"><u><font size="+1">Compatibility</font></u></font></p>
<p>This design should be fully software compatible to the Microchip Implementation 
  of the PIC 16C57, except for the following extensions:</p>
<ul>
  <li>Port A is full 8 bits wide</li>
  <li>Hardware stack is 4 level deep [original 2 levels] (can be easily expanded)</li>
  <li>Executions of instructions that modify the PC has became a lot more expensive 
    due to the pipeline and execution of instructions on every cycle. Any instruction 
    that writes to the PC (PC as destination (f), call, goto, retlw) now takes 
    4 cycles to execute (instead of 2 in the original implementation).<br>
    The 4 'skip' instructions, remain as in the original implementation: 1 cycle 
    if not skipped, 2 cycles if skipped.</li>
  <li>Sampling of IO ports might be off</li>
  <li>Timer and watchdog might be off a few cycles<font size="+1"> </font></li>
</ul>
<p><font size="+2"><u><font size="+1">Performance</font></u></font><u></u></p>
<ul>
  <li>Single cycle instruction execution, except as noted above for PC modifications.</li>
  <li>I estimate about 22K gates with the xilinx primitives, (excluding Register 
    File and Program Memory). A Xilinx Vertex XCV100 can hold 4 of this cores 
    and program memory, and still have some room left.</li>
</ul>
<p><font size="+2"><u><font size="+1">Implementing the Core</font></u></font></p>
<p>The only file you should edit if you really want to implement this core, is 
  the 'primitives.v' file. It contains all parts that can be optimized, depending 
  on the technology used. It includes memories, and arithmetic modules. I added 
  a primitives_xilinx,v file and xilinx_primitives.zip which contain primitives 
  for xilinx.</p>
<p></p>
<p><font size="+1"><u>Status</u></font></p>
<p>First version of the core is released. Included with the release is also a 
  small test bench and several test programs written in assembly. MPLAB from Microchip, 
  can be used to compile and develop additional code.</p>
<p>The core can be downloaded from OpenCores CVS via <a href="http://www.opencores.org/cvsweb.shtml/">cvsweb</a> 
  or via <a href="/cvsmodule.shtml">cvsget</a> (use minirisc for module name)<font size="+1"> 
  </font></p>
<p><font size="+1"><u>Development Tools</u></font></p>
<p>A very nice(and free) development environment with a software simulator is 
  provided by Microchip on their web site. This environment works only on PCs. 
  Various free and chimerical tools are available from third party, just Search 
  the web !</p>
<p><a href="http://www.microchip.com/10/Tools/PICmicro/DevEnv/">Here is a link 
  to the Microchip Development environment</a> (http://www.microchip.com/10/Tools/PICmicro/DevEnv/)</p>
<p><font size="+1"><u>To-Do</u></font></p>
<p>Things that need to be done</p>
<ol>
  <li>Write more test/compliance test vectors 
    <ul>
      <li> Verify that all instructions after a goto/call/retlw/write to PCL are 
        not executed</li>
      <li> Verify ALU</li>
      <li> Timer and Watchdog tests</li>
    </ul>
  </li>
  <ul>
    <li> Perhaps some other areas ?</li>
  </ul>
  <li>Extensions ? 
    <ul>
      <li> guess this is on a "as needed" basis</li>
      <li>Would be nice to extend the register file and have a few registers that 
        are shared between two or more of this cores in a MP implementation !</li>
    </ul>
  </li>
</ol>
<p><font size="+2"><u><font size="+1">Author / Maintainer</font></u></font></p>
<p>I have been doing ASIC design, verification and synthesis for over 15 years. 
  This core is only a "midnight hack", and should be used with caution. I'd also 
  like to know if anyone will actually use this core. Please send me a note if 
  you will !</p>
<p>Rudolf Usselmann <a href="mailto:rudi@asics.ws_NOSPAM">rudi@asics.ws_NOSPAM</a></p>
<p>Feel free to send me comments, suggestions and bug reports.</p>
<P><FONT FACE="Times"></FONT><font size="+2"><u><font size="+1">Change Log</font></u></font></P>
<p>6/18/200 RU<br>
  - Added this Change Log<br>
  - Added "Development Tools" Section|<br>
  - Removed speed claims from the "Performance" Section: Need to re-synthsise 
  the core and resolve synthesis tool/backend tool issues.<br>
  - added "risc_core_top.v", a top level with tri-state buffers and 
  program memory, to make it look like a real PIC !<br>
  - Updated the primitives_xilinx.v so it will work correctly with Synplify and 
  Synopsys FPGA compiler</p>
 
 
 
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