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[/] [miniuart2/] [trunk/] [impl/] [Xilinx_xc2s15/] [uart.mrp] - Rev 26

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Release 4.2i - Map E.35
Xilinx Mapping Report File for Design 'uart'

Design Information
------------------
Command Line   : map -p xc2s15-cs144-6 -cm area -k 4 -c 100 -tx off uart.ngd 
Target Device  : x2s15
Target Package : cs144
Target Speed   : -6
Mapper Version : spartan2 -- $Revision: 1.1.1.1 $
Mapped Date    : Thu Jan 09 18:11:05 2003

Design Summary
--------------
   Number of errors:      0
   Number of warnings:    0
   Number of Slices:                 83 out of    192   43%
   Number of Slices containing
      unrelated logic:                0 out of     83    0%
   Number of Slice Flip Flops:       63 out of    384   16%
   Total Number 4 input LUTs:       115 out of    384   29%
      Number used as LUTs:                        110
      Number used as a route-thru:                  5
   Number of bonded IOBs:            26 out of     86   30%
      IOB Flip Flops:                               9
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
Total equivalent gate count for design:  1,329
Additional JTAG gate count for IOBs:  1,344

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------

Section 3 - Informational
-------------------------
INFO:MapLib:62 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.

Section 4 - Removed Logic Summary
---------------------------------
   2 block(s) optimized away

Section 5 - Removed Logic
-------------------------

Optimized Block(s):
TYPE            BLOCK
GND             GND_I
VCC             VCC_I

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| br_clk_i                           | GCLKIOB | INPUT     | LVTTL       |          |      |          |          |       |
| wb_clk_i                           | GCLKIOB | INPUT     | LVTTL       |          |      |          |          |       |
| intrx_o                            | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       |
| inttx_o                            | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| rxd_pad_i                          | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| txd_pad_o                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| wb_ack_o                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| wb_adr_i<0>                        | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| wb_adr_i<1>                        | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| wb_dat_i<0>                        | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | DELAY |
| wb_dat_i<1>                        | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | DELAY |
| wb_dat_i<2>                        | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | DELAY |
| wb_dat_i<3>                        | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | DELAY |
| wb_dat_i<4>                        | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | DELAY |
| wb_dat_i<5>                        | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | DELAY |
| wb_dat_i<6>                        | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | DELAY |
| wb_dat_i<7>                        | IOB     | INPUT     | LVTTL       |          |      | INFF     |          | DELAY |
| wb_dat_o<0>                        | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| wb_dat_o<1>                        | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| wb_dat_o<2>                        | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| wb_dat_o<3>                        | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| wb_dat_o<4>                        | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| wb_dat_o<5>                        | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| wb_dat_o<6>                        | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| wb_dat_o<7>                        | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| wb_rst_i                           | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| wb_stb_i                           | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| wb_we_i                            | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
+------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group Summary
------------------------------
No area groups were found in this design.

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.

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