URL
https://opencores.org/ocsvn/miniuart2/miniuart2/trunk
Subversion Repositories miniuart2
[/] [miniuart2/] [trunk/] [impl/] [Xilinx_xc2s15/] [uart.pad] - Rev 22
Go to most recent revision | Compare with Previous | Blame | View Log
Release 4.2i - Par E.35Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.Thu Jan 09 18:11:11 2003Xilinx PAD Specification File*****************************Input file: par_temp.ncdOutput file: uart.ncdPart type: xc2s15Speed grade: -6Package: cs144Pinout by Signal Name:--------------------------|-----------------|--------|-----------|-------------|----------|----------|------|----------|-----------|---------|-----------|Signal Name | Pin Name | Pin | Direction | IO Standard |IO Bank # |Drive (mA)| Slew | Pullup | IOB Delay | Voltage |Constraint || | Number | | | | | Rate | Pulldown | | | |--------------------------|-----------------|--------|-----------|-------------|----------|----------|------|----------|-----------|---------|-----------|br_clk_i | | M7 | INPUT | LVTTL | 5 | 12* | SLOW*| NONE** | *** | | |intrx_o | | N8 | OUTPUT | LVTTL | 4 | 12 | SLOW | NONE** | *** | | |inttx_o | | K6 | OUTPUT | LVTTL | 5 | 12 | SLOW | NONE** | *** | | |rxd_pad_i | | C6 | INPUT | LVTTL | 0 | 12* | SLOW*| NONE** | NONE | | |txd_pad_o | VREF | L8 | OUTPUT | LVTTL | 4 | 12 | SLOW | NONE** | *** | | |wb_ack_o | | M8 | OUTPUT | LVTTL | 4 | 12 | SLOW | NONE** | *** | | |wb_adr_i<0> | | K4 | INPUT | LVTTL | 5 | 12* | SLOW*| NONE** | NONE | | |wb_adr_i<1> | | H4 | INPUT | LVTTL | 6 | 12* | SLOW*| NONE** | NONE | | |wb_clk_i | | K7 | INPUT | LVTTL | 4 | 12* | SLOW*| NONE** | *** | | |wb_dat_i<0> | | C8 | INPUT | LVTTL | 1 | 12* | SLOW*| NONE** | IFD | | |wb_dat_i<1> | | D8 | INPUT | LVTTL | 1 | 12* | SLOW*| NONE** | IFD | | |wb_dat_i<2> | | N10 | INPUT | LVTTL | 4 | 12* | SLOW*| NONE** | IFD | | |wb_dat_i<3> | | K9 | INPUT | LVTTL | 4 | 12* | SLOW*| NONE** | IFD | | |wb_dat_i<4> | | N9 | INPUT | LVTTL | 4 | 12* | SLOW*| NONE** | IFD | | |wb_dat_i<5> | | K8 | INPUT | LVTTL | 4 | 12* | SLOW*| NONE** | IFD | | |wb_dat_i<6> | | D9 | INPUT | LVTTL | 1 | 12* | SLOW*| NONE** | IFD | | |wb_dat_i<7> | | C9 | INPUT | LVTTL | 1 | 12* | SLOW*| NONE** | IFD | | |wb_dat_o<0> | VREF | L6 | OUTPUT | LVTTL | 5 | 12 | SLOW | NONE** | *** | | |wb_dat_o<1> | | H3 | OUTPUT | LVTTL | 6 | 12 | SLOW | NONE** | *** | | |wb_dat_o<2> | | J2 | OUTPUT | LVTTL | 6 | 12 | SLOW | NONE** | *** | | |wb_dat_o<3> | | K2 | OUTPUT | LVTTL | 6 | 12 | SLOW | NONE** | *** | | |wb_dat_o<4> | VREF | H2 | OUTPUT | LVTTL | 6 | 12 | SLOW | NONE** | *** | | |wb_dat_o<5> | VREF | K1 | OUTPUT | LVTTL | 6 | 12 | SLOW | NONE** | *** | | |wb_dat_o<6> | | J3 | OUTPUT | LVTTL | 6 | 12 | SLOW | NONE** | *** | | |wb_dat_o<7> | VREF | L4 | OUTPUT | LVTTL | 5 | 12 | SLOW | NONE** | *** | | |wb_rst_i | | N11 | INPUT | LVTTL | 4 | 12* | SLOW*| NONE** | NONE | | |wb_stb_i | DOUT_BUSY | C11 | INPUT | LVTTL | 2 | 12* | SLOW*| NONE** | NONE | | |wb_we_i | | M6 | INPUT | LVTTL | 5 | 12* | SLOW*| NONE** | NONE | | |--------------------------|-----------------|--------|-----------|-------------|----------|----------|------|----------|-----------|---------|-----------|Pinout by Pin Number:--------|--------------------------|-----------------|-----------|-------------|----------|----------|------|----------|-----------|---------|-----------|Pin | Signal Name | Pin Name | Direction | IO Standard |IO Bank # |Drive (mA)| Slew | Pullup | IOB Delay | Voltage |Constraint |Number | | | | | | | Rate | Pulldown | | | |--------|--------------------------|-----------------|-----------|-------------|----------|----------|------|----------|-----------|---------|-----------|A1 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |A2 | | VCCO | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |A3 | | | UNUSED | LVTTL* | 0 | 12* | SLOW*| NONE** | *** | | |A4 | | | UNUSED | LVTTL* | 0 | 12* | SLOW*| NONE** | *** | | |A5 | | | UNUSED | LVTTL* | 0 | 12* | SLOW*| NONE** | *** | | |A6 | | | UNUSED | LVTTL* | 0 | 12* | SLOW*| NONE** | *** | | |A7 | | | UNUSED | LVTTL* | 1 | 12* | SLOW*| NONE** | *** | | |A8 | | | UNUSED | LVTTL* | 1 | 12* | SLOW*| NONE** | *** | | |A9 | | VCCINT | | LVTTL* | | 12* | SLOW*| NONE** | *** | 2.5 | |A10 | | VREF | | LVTTL* | 1 | 12* | SLOW*| NONE** | *** | | |A11 | | TDI | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |A12 | | TDO | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |A13 | | VCCO | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |B1 | | TMS | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |B2 | | VCCO | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |B3 | | | UNUSED | LVTTL* | 0 | 12* | SLOW*| NONE** | *** | | |B4 | | | UNUSED | LVTTL* | 0 | 12* | SLOW*| NONE** | *** | | |B5 | | | UNUSED | LVTTL* | 0 | 12* | SLOW*| NONE** | *** | | |B6 | | VCCINT | | LVTTL* | | 12* | SLOW*| NONE** | *** | 2.5 | |B7 | | | UNUSED | LVTTL* | 1 | 12* | SLOW*| NONE** | *** | | |B8 | | VREF | | LVTTL* | 1 | 12* | SLOW*| NONE** | *** | | |B9 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |B10 | | | UNUSED | LVTTL* | 1 | 12* | SLOW*| NONE** | *** | | |B11 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |B12 | | VCCO | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |B13 | | CCLK | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |C1 | | | UNUSED | LVTTL* | 7 | 12* | SLOW*| NONE** | *** | | |C2 | | | UNUSED | LVTTL* | 7 | 12* | SLOW*| NONE** | *** | | |C3 | | TCK | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |C4 | | VREF | | LVTTL* | 0 | 12* | SLOW*| NONE** | *** | | |C5 | | VCCINT | | LVTTL* | | 12* | SLOW*| NONE** | *** | 2.5 | |C6 | rxd_pad_i | | INPUT | LVTTL | 0 | 12* | SLOW*| NONE** | NONE | | |C7 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |C8 | wb_dat_i<0> | | INPUT | LVTTL | 1 | 12* | SLOW*| NONE** | IFD | | |C9 | wb_dat_i<7> | | INPUT | LVTTL | 1 | 12* | SLOW*| NONE** | IFD | | |C10 | | WRITE | | LVTTL* | 1 | 12* | SLOW*| NONE** | *** | | |C11 | wb_stb_i | DOUT_BUSY | INPUT | LVTTL | 2 | 12* | SLOW*| NONE** | NONE | | |C12 | | DIN_D0 | | LVTTL* | 2 | 12* | SLOW*| NONE** | *** | | |C13 | | | UNUSED | LVTTL* | 2 | 12* | SLOW*| NONE** | *** | | |D1 | | | UNUSED | LVTTL* | 7 | 12* | SLOW*| NONE** | *** | | |D2 | | | UNUSED | LVTTL* | 7 | 12* | SLOW*| NONE** | *** | | |D3 | | NC | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |D4 | | VREF | | LVTTL* | 7 | 12* | SLOW*| NONE** | *** | | |D5 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |D6 | | VREF | | LVTTL* | 0 | 12* | SLOW*| NONE** | *** | | |D7 | | VCCO | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |D8 | wb_dat_i<1> | | INPUT | LVTTL | 1 | 12* | SLOW*| NONE** | IFD | | |D9 | wb_dat_i<6> | | INPUT | LVTTL | 1 | 12* | SLOW*| NONE** | IFD | | |D10 | | CS | | LVTTL* | 1 | 12* | SLOW*| NONE** | *** | | |D11 | | VREF | | LVTTL* | 2 | 12* | SLOW*| NONE** | *** | | |D12 | | NC | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |D13 | | | UNUSED | LVTTL* | 2 | 12* | SLOW*| NONE** | *** | | |E1 | | VREF | | LVTTL* | 7 | 12* | SLOW*| NONE** | *** | | |E2 | | | UNUSED | LVTTL* | 7 | 12* | SLOW*| NONE** | *** | | |E3 | | | UNUSED | LVTTL* | 7 | 12* | SLOW*| NONE** | *** | | |E4 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |E10 | | D1 | | LVTTL* | 2 | 12* | SLOW*| NONE** | *** | | |E11 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |E12 | | D2 | | LVTTL* | 2 | 12* | SLOW*| NONE** | *** | | |E13 | | | UNUSED | LVTTL* | 2 | 12* | SLOW*| NONE** | *** | | |F1 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |F2 | | IRDY | | LVTTL* | 7 | 12* | SLOW*| NONE** | *** | | |F3 | | | UNUSED | LVTTL* | 7 | 12* | SLOW*| NONE** | *** | | |F4 | | | UNUSED | LVTTL* | 7 | 12* | SLOW*| NONE** | *** | | |F10 | | VREF | | LVTTL* | 2 | 12* | SLOW*| NONE** | *** | | |F11 | | D3 | | LVTTL* | 2 | 12* | SLOW*| NONE** | *** | | |F12 | | | UNUSED | LVTTL* | 2 | 12* | SLOW*| NONE** | *** | | |F13 | | IRDY | | LVTTL* | 2 | 12* | SLOW*| NONE** | *** | | |G1 | | TRDY | | LVTTL* | 6 | 12* | SLOW*| NONE** | *** | | |G2 | | VCCO | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |G3 | | VCCINT | | LVTTL* | | 12* | SLOW*| NONE** | *** | 2.5 | |G4 | | | UNUSED | LVTTL* | 6 | 12* | SLOW*| NONE** | *** | | |G10 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |G11 | | VCCO | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |G12 | | VCCINT | | LVTTL* | | 12* | SLOW*| NONE** | *** | 2.5 | |G13 | | TRDY | | LVTTL* | 3 | 12* | SLOW*| NONE** | *** | | |H1 | | | UNUSED | LVTTL* | 6 | 12* | SLOW*| NONE** | *** | | |H2 | wb_dat_o<4> | VREF | OUTPUT | LVTTL | 6 | 12 | SLOW | NONE** | *** | | |H3 | wb_dat_o<1> | | OUTPUT | LVTTL | 6 | 12 | SLOW | NONE** | *** | | |H4 | wb_adr_i<1> | | INPUT | LVTTL | 6 | 12* | SLOW*| NONE** | NONE | | |H10 | | | UNUSED | LVTTL* | 3 | 12* | SLOW*| NONE** | *** | | |H11 | | VREF | | LVTTL* | 3 | 12* | SLOW*| NONE** | *** | | |H12 | | D4 | | LVTTL* | 3 | 12* | SLOW*| NONE** | *** | | |H13 | | | UNUSED | LVTTL* | 3 | 12* | SLOW*| NONE** | *** | | |J1 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |J2 | wb_dat_o<2> | | OUTPUT | LVTTL | 6 | 12 | SLOW | NONE** | *** | | |J3 | wb_dat_o<6> | | OUTPUT | LVTTL | 6 | 12 | SLOW | NONE** | *** | | |J4 | | NC | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |J10 | | | UNUSED | LVTTL* | 3 | 12* | SLOW*| NONE** | *** | | |J11 | | D6 | | LVTTL* | 3 | 12* | SLOW*| NONE** | *** | | |J12 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |J13 | | D5 | | LVTTL* | 3 | 12* | SLOW*| NONE** | *** | | |K1 | wb_dat_o<5> | VREF | OUTPUT | LVTTL | 6 | 12 | SLOW | NONE** | *** | | |K2 | wb_dat_o<3> | | OUTPUT | LVTTL | 6 | 12 | SLOW | NONE** | *** | | |K3 | | | UNUSED | LVTTL* | 6 | 12* | SLOW*| NONE** | *** | | |K4 | wb_adr_i<0> | | INPUT | LVTTL | 5 | 12* | SLOW*| NONE** | NONE | | |K5 | | | UNUSED | LVTTL* | 5 | 12* | SLOW*| NONE** | *** | | |K6 | inttx_o | | OUTPUT | LVTTL | 5 | 12 | SLOW | NONE** | *** | | |K7 | wb_clk_i | | INPUT | LVTTL | 4 | 12* | SLOW*| NONE** | *** | | |K8 | wb_dat_i<5> | | INPUT | LVTTL | 4 | 12* | SLOW*| NONE** | IFD | | |K9 | wb_dat_i<3> | | INPUT | LVTTL | 4 | 12* | SLOW*| NONE** | IFD | | |K10 | | D7 | | LVTTL* | 3 | 12* | SLOW*| NONE** | *** | | |K11 | | | UNUSED | LVTTL* | 3 | 12* | SLOW*| NONE** | *** | | |K12 | | VREF | | LVTTL* | 3 | 12* | SLOW*| NONE** | *** | | |K13 | | NC | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |L1 | | | UNUSED | LVTTL* | 6 | 12* | SLOW*| NONE** | *** | | |L2 | | M1 | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |L3 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |L4 | wb_dat_o<7> | VREF | OUTPUT | LVTTL | 5 | 12 | SLOW | NONE** | *** | | |L5 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |L6 | wb_dat_o<0> | VREF | OUTPUT | LVTTL | 5 | 12 | SLOW | NONE** | *** | | |L7 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |L8 | txd_pad_o | VREF | OUTPUT | LVTTL | 4 | 12 | SLOW | NONE** | *** | | |L9 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |L10 | | VREF | | LVTTL* | 4 | 12* | SLOW*| NONE** | *** | | |L11 | | | UNUSED | LVTTL* | 4 | 12* | SLOW*| NONE** | *** | | |L12 | | PROGRAM | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |L13 | | INIT | | LVTTL* | 3 | 12* | SLOW*| NONE** | *** | | |M1 | | M0 | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |M2 | | VCCO | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |M4 | | NC | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |M5 | | VCCINT | | LVTTL* | | 12* | SLOW*| NONE** | *** | 2.5 | |M6 | wb_we_i | | INPUT | LVTTL | 5 | 12* | SLOW*| NONE** | NONE | | |M7 | br_clk_i | | INPUT | LVTTL | 5 | 12* | SLOW*| NONE** | *** | | |M8 | wb_ack_o | | OUTPUT | LVTTL | 4 | 12 | SLOW | NONE** | *** | | |M9 | | VCCINT | | LVTTL* | | 12* | SLOW*| NONE** | *** | 2.5 | |M10 | | NC | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |M11 | | | UNUSED | LVTTL* | 4 | 12* | SLOW*| NONE** | *** | | |M12 | | DONE | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |M13 | | VCCO | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |N1 | | VCCO | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |N2 | | M2 | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |N4 | | | UNUSED | LVTTL* | 5 | 12* | SLOW*| NONE** | *** | | |N5 | | | UNUSED | LVTTL* | 5 | 12* | SLOW*| NONE** | *** | | |N6 | | VCCINT | | LVTTL* | | 12* | SLOW*| NONE** | *** | 2.5 | |N7 | | VCCO | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |N8 | intrx_o | | OUTPUT | LVTTL | 4 | 12 | SLOW | NONE** | *** | | |N9 | wb_dat_i<4> | | INPUT | LVTTL | 4 | 12* | SLOW*| NONE** | IFD | | |N10 | wb_dat_i<2> | | INPUT | LVTTL | 4 | 12* | SLOW*| NONE** | IFD | | |N11 | wb_rst_i | | INPUT | LVTTL | 4 | 12* | SLOW*| NONE** | NONE | | |N12 | | GND | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |N13 | | VCCO | | LVTTL* | | 12* | SLOW*| NONE** | *** | | |--------|--------------------------|-----------------|-----------|-------------|----------|----------|------|----------|-----------|---------|-----------|* Default value.** This default Pullup/Pulldown value can be overridden in Bitgen.*** The default IOB Delay is determined by how the IOB is used.## To preserve the pinout above for future design iterations,# simply invoke PIN2UCF from the command line or issue this command in the GUI.# For Foundation ISE/Project Navigator - Run the process "Implement Design" -> "Place-and-Route" -> "Back-annotate Pin Locations"# For Design Manager - In the Design menu select "Lock Pins...# The location constraints above will be written into your specified UCF file. (The constraints# listed below are in PCF format and cannot be directly used in the UCF file).#COMP "br_clk_i" LOCATE = SITE "M7" ;COMP "intrx_o" LOCATE = SITE "N8" ;COMP "inttx_o" LOCATE = SITE "K6" ;COMP "rxd_pad_i" LOCATE = SITE "C6" ;COMP "txd_pad_o" LOCATE = SITE "L8" ;COMP "wb_ack_o" LOCATE = SITE "M8" ;COMP "wb_adr_i<0>" LOCATE = SITE "K4" ;COMP "wb_adr_i<1>" LOCATE = SITE "H4" ;COMP "wb_clk_i" LOCATE = SITE "K7" ;COMP "wb_dat_i<0>" LOCATE = SITE "C8" ;COMP "wb_dat_i<1>" LOCATE = SITE "D8" ;COMP "wb_dat_i<2>" LOCATE = SITE "N10" ;COMP "wb_dat_i<3>" LOCATE = SITE "K9" ;COMP "wb_dat_i<4>" LOCATE = SITE "N9" ;COMP "wb_dat_i<5>" LOCATE = SITE "K8" ;COMP "wb_dat_i<6>" LOCATE = SITE "D9" ;COMP "wb_dat_i<7>" LOCATE = SITE "C9" ;COMP "wb_dat_o<0>" LOCATE = SITE "L6" ;COMP "wb_dat_o<1>" LOCATE = SITE "H3" ;COMP "wb_dat_o<2>" LOCATE = SITE "J2" ;COMP "wb_dat_o<3>" LOCATE = SITE "K2" ;COMP "wb_dat_o<4>" LOCATE = SITE "H2" ;COMP "wb_dat_o<5>" LOCATE = SITE "K1" ;COMP "wb_dat_o<6>" LOCATE = SITE "J3" ;COMP "wb_dat_o<7>" LOCATE = SITE "L4" ;COMP "wb_rst_i" LOCATE = SITE "N11" ;COMP "wb_stb_i" LOCATE = SITE "C11" ;COMP "wb_we_i" LOCATE = SITE "M6" ;#
Go to most recent revision | Compare with Previous | Blame | View Log