Subversion Repositories miniuart2

Release 4.2i - Par E.35
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.


Thu Jan 09 18:11:08 2003

par -f _par.rsp


Constraints file: uart.pcf

Loading design for application par from file par_temp.ncd.
   "uart" is an NCD, version 2.37, device xc2s15, package cs144, speed -6
Loading device for application par from file '2s15.nph' in environment e:/ise.
Device speed data version:  PRELIMINARY 1.23 2001-12-19.


Device utilization summary:

   Number of External GCLKIOBs         2 out of 4      50%
   Number of External IOBs            26 out of 86     30%
      Number of LOCed External IOBs    0 out of 26      0%

   Number of SLICEs                   83 out of 192    43%

   Number of GCLKs                     2 out of 4      50%



Overall effort level (-ol):   2 (set by user)
Placer effort level (-pl):    2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    2 (set by user)
Extra effort level (-xe):     0 (set by user)

Starting initial Placement phase. REAL time: 0 secs 
Finished initial Placement phase. REAL time: 0 secs 
Starting the placer. REAL time: 0 secs 
Placement pass 1 ....
Placer score = 7875
Placement pass 2 ...............
Placer score = 7375
Optimizing ... 
Placer score = 6385
Placer score = 5890
Placer completed in real time: 0 secs 

Dumping design to file uart.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 1 secs 

0 connection(s) routed; 522 unrouted active, 4 unrouted PWR/GND.
Starting router resource preassignment
Completed router resource preassignment. REAL time: 0 secs 
Starting iterative routing. 
Routing active signals.
.....
End of iteration 1 
526 successful; 0 unrouted; (0) REAL time: 0 secs 
Constraints are met. 
Total REAL time: 2 secs 
Total CPU  time: 1 secs 
End of route.  526 routed (100.00%); 0 unrouted.
No errors found. 
Completely routed. 

This design was run without timing constraints.  It is likely that much better
circuit performance can be obtained by trying either or both of the following:

  - Enabling the Delay Based Cleanup router pass, if not already enabled
  - Supplying timing constraints in the input design


Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 1 secs 

Generating PAR statistics.

   The Delay Summary Report

   The Score for this design is: 132


The Number of signals not completely routed for this design is: 0

   The Average Connection Delay for this design is:        1.010 ns
   The Maximum Pin Delay is:                               2.509 ns
   The Average Connection Delay on the 10 Worst Nets is:   1.597 ns

   Listing Pin Delays by value: (ns)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         258         259           9           0           0           0

Dumping design to file uart.ncd.


All signals are completely routed.

Total REAL time to PAR completion: 4 secs 
Total CPU time to PAR completion: 1 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.

PAR done.