Subversion Repositories miniuart2

Release 4.2i - xst E.35
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
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--> =========================================================================
---- Source Parameters
Input Format                       : VHDL
Input File Name                    : uart.prj

---- Target Parameters
Target Device                      : xc2s15-cs144-6
Output File Name                   : uart
Output Format                      : NGC
Target Technology                  : spartan2

---- Source Options
Entity Name                        : uart
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
ROM Extraction                     : Yes
RAM Extraction                     : Yes
RAM Style                          : Auto
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Add Generic Clock Buffer(BUFG)     : 4
Global Maximum Fanout              : 100
Register Duplication               : YES
Move First FlipFlop Stage          : YES
Move Last FlipFlop Stage           : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Speed Grade                        : 6

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : No
Global Optimization                : AllClockNets
Write Timing Constraints           : No

=========================================================================

Compiling vhdl file J:/impl/../rtl/vhdl/utils.vhd in Library work.
Entity <synchroniser> (Architecture <behaviour>) compiled.
Entity <counter> (Architecture <behaviour>) compiled.
Compiling vhdl file J:/impl/../rtl/vhdl/Txunit.vhd in Library work.
Entity <txunit> (Architecture <behaviour>) compiled.
Compiling vhdl file J:/impl/../rtl/vhdl/Rxunit.vhd in Library work.
Entity <rxunit> (Architecture <behaviour>) compiled.
Compiling vhdl file J:/impl/../rtl/vhdl/miniuart.vhd in Library work.
Entity <uart> (Architecture <behaviour>) compiled.

Analyzing Entity <uart> (Architecture <behaviour>).
Entity <uart> analyzed. Unit <uart> generated.

Analyzing generic Entity <counter> (Architecture <behaviour>).
        count = 130
Entity <counter> analyzed. Unit <counter> generated.

Analyzing generic Entity <counter> (Architecture <behaviour>).
        count = 4
Entity <counter> analyzed. Unit <counter0> generated.

Analyzing Entity <txunit> (Architecture <behaviour>).
Entity <txunit> analyzed. Unit <txunit> generated.

Analyzing Entity <rxunit> (Architecture <behaviour>).
Entity <rxunit> analyzed. Unit <rxunit> generated.

Analyzing Entity <synchroniser> (Architecture <behaviour>).
Entity <synchroniser> analyzed. Unit <synchroniser> generated.


Synthesizing Unit <synchroniser>.
    Related source file is J:/impl/../rtl/vhdl/utils.vhd.
    Found 1-bit register for signal <c1a>.
    Found 1-bit register for signal <c1s>.
    Found 1-bit register for signal <r>.
    Summary:
        inferred   3 D-type flip-flop(s).
Unit <synchroniser> synthesized.


Synthesizing Unit <rxunit>.
    Related source file is J:/impl/../rtl/vhdl/Rxunit.vhd.
    Found 1-bit register for signal <rxav>.
    Found 8-bit register for signal <datao>.
    Found 2-bit adder for signal <$n0002> created at line 91.
    Found 4-bit adder for signal <$n0018> created at line 85.
    Found 4-bit comparator greatequal for signal <$n0038> created at line 81.
    Found 4-bit register for signal <bitpos>.
    Found 8-bit register for signal <rreg>.
    Found 1-bit register for signal <rregl>.
    Found 2-bit register for signal <samplecnt>.
    Summary:
        inferred  24 D-type flip-flop(s).
        inferred   2 Adder/Subtracter(s).
        inferred   1 Comparator(s).
Unit <rxunit> synthesized.


Synthesizing Unit <txunit>.
    Related source file is J:/impl/../rtl/vhdl/Txunit.vhd.
    Found 1-bit register for signal <txd>.
    Found 4-bit adder for signal <$n0012> created at line 92.
    Found 4-bit register for signal <bitpos>.
    Found 8-bit register for signal <tbuff>.
    Found 1-bit register for signal <tbufl>.
    Found 8-bit register for signal <treg>.
    Summary:
        inferred  22 D-type flip-flop(s).
        inferred   1 Adder/Subtracter(s).
Unit <txunit> synthesized.


Synthesizing Unit <counter0>.
    Related source file is J:/impl/../rtl/vhdl/utils.vhd.
    Found 1-bit register for signal <o>.
    Found 2-bit down counter for signal <cnt>.
WARNING:Xst:647 - Input <reset> is never used.
    Summary:
        inferred   1 Counter(s).
        inferred   1 D-type flip-flop(s).
Unit <counter0> synthesized.


Synthesizing Unit <counter>.
    Related source file is J:/impl/../rtl/vhdl/utils.vhd.
    Found 1-bit register for signal <o>.
    Found 8-bit down counter for signal <cnt>.
WARNING:Xst:647 - Input <reset> is never used.
WARNING:Xst:647 - Input <ce> is never used.
    Summary:
        inferred   1 Counter(s).
        inferred   1 D-type flip-flop(s).
Unit <counter> synthesized.


Synthesizing Unit <uart>.
    Related source file is J:/impl/../rtl/vhdl/miniuart.vhd.
WARNING:Xst:646 - Signal <sig0> is assigned but never used.
WARNING:Xst:646 - Signal <sig1> is assigned but never used.
    Found 1-bit register for signal <loada>.
    Found 1-bit register for signal <reada>.
    Found 8-bit register for signal <txdata>.
    Summary:
        inferred  10 D-type flip-flop(s).
Unit <uart> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 26
  4-bit register                   : 2
  2-bit register                   : 1
  8-bit register                   : 4
  1-bit register                   : 19
# Counters                         : 2
  2-bit down counter               : 1
  8-bit down counter               : 1
# Adders/Subtractors               : 3
  2-bit adder                      : 1
  4-bit adder                      : 2
# Comparators                      : 1
  4-bit comparator greatequal      : 1

=========================================================================


Starting low level synthesis...
Optimizing unit <counter> ...

Optimizing unit <rxunit> ...

Optimizing unit <txunit> ...

Optimizing unit <uart> ...

Building and optimizing final netlist ...

FlipFlop uart_rxunit_rxav has been replicated 1 time(s) to handle iob=true attribute.
=========================================================================
Final Results
Top Level Output File Name         : uart
Output Format                      : NGC
Optimization Criterion             : Speed
Target Technology                  : spartan2
Keep Hierarchy                     : No
Macro Generator                    : macro+

Macro Statistics
# Registers                        : 35
  4-bit register                   : 2
  8-bit register                   : 4
  2-bit register                   : 2
  1-bit register                   : 27
# Adders/Subtractors               : 3
  4-bit adder                      : 2
  8-bit subtractor                 : 1

Design Statistics
# IOs                              : 28

Cell Usage :
# BELS                             : 153
#      GND                         : 1
#      LUT1                        : 13
#      LUT1_D                      : 2
#      LUT1_L                      : 3
#      LUT2                        : 21
#      LUT3                        : 24
#      LUT3_L                      : 2
#      LUT4                        : 51
#      LUT4_D                      : 2
#      LUT4_L                      : 2
#      MUXCY                       : 13
#      MUXF5                       : 4
#      VCC                         : 1
#      XORCY                       : 14
# FlipFlops/Latches                : 72
#      FDC                         : 4
#      FDCE                        : 10
#      FDE                         : 40
#      FDPE                        : 1
#      FDR                         : 11
#      FDRE                        : 2
#      FDS                         : 2
#      FDSE                        : 2
# Clock Buffers                    : 2
#      BUFGP                       : 2
# IO Buffers                       : 26
#      IBUF                        : 14
#      OBUF                        : 12
=========================================================================


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
uart_rxunit_rregl:Q                | NONE                   | 3     |
br_clk_i                           | BUFGP                  | 59    |
loada:Q                            | NONE                   | 1     |
wb_clk_i                           | BUFGP                  | 10    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.318ns (Maximum Frequency: 107.319MHz)
   Minimum input arrival time before clock: 8.430ns
   Maximum output required time after clock: 10.658ns
   Maximum combinational path delay: 9.098ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'br_clk_i'
Delay:               9.318ns (Levels of Logic = 6)
  Source:            uart_rxunit_bitpos_0
  Destination:       uart_rxunit_bitpos_2
  Source Clock:      br_clk_i rising
  Destination Clock: br_clk_i rising

  Data Path: uart_rxunit_bitpos_0 to uart_rxunit_bitpos_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    FDCE:C->Q             22   1.085   2.970  uart_rxunit_bitpos_0 (uart_rxunit_bitpos_0)
    LUT1_D:I0->LO          1   0.549   0.000  uart_rxunit_Madd__n0018_inst_lut2_0 (N3009)
    MUXCY:S->O             1   0.659   0.000  uart_rxunit_Madd__n0018_inst_cy_0 (uart_rxunit_Madd__n0018_inst_cy_0)
    MUXCY:CI->O            1   0.042   0.000  uart_rxunit_Madd__n0018_inst_cy_1 (uart_rxunit_Madd__n0018_inst_cy_1)
    XORCY:CI->O            1   0.420   1.035  uart_rxunit_Madd__n0018_inst_sum_2 (uart_rxunit_N181)
    LUT4:I3->O             1   0.549   1.035  uart_rxunit_I_10_LUT_53 (uart_rxunit_N183)
    LUT4_L:I0->LO          1   0.549   0.000  uart_rxunit_I__n0005_2 (uart_rxunit_N201)
    FDCE:D                     0.425          uart_rxunit_bitpos_2
    ----------------------------------------
    Total                      9.318ns (4.278ns logic, 5.040ns route)
                                       (45.9% logic, 54.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'br_clk_i'
Offset:              8.430ns (Levels of Logic = 3)
  Source:            wb_rst_i
  Destination:       uart_txunit_treg_5
  Destination Clock: br_clk_i rising

  Data Path: wb_rst_i to uart_txunit_treg_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    IBUF:I->O             19   0.776   2.790  wb_rst_i_IBUF (wb_rst_i_IBUF)
    LUT4:I3->O             1   0.549   1.035  uart_txunit_I_1_LUT_11 (N2973)
    LUT4:I3->O             8   0.549   1.845  uart_txunit_I__n0009 (uart_txunit_N83)
    FDE:CE                     0.886          uart_txunit_treg_5
    ----------------------------------------
    Total                      8.430ns (2.760ns logic, 5.670ns route)
                                       (32.7% logic, 67.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'br_clk_i'
Offset:              10.658ns (Levels of Logic = 3)
  Source:            uart_txunit_tbufl
  Destination:       wb_dat_o_0
  Source Clock:      br_clk_i rising

  Data Path: uart_txunit_tbufl to wb_dat_o_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    FDCE:C->Q              5   1.085   1.566  uart_txunit_tbufl (uart_txunit_tbufl)
    LUT2:I1->O             2   0.549   1.206  uart_txunit_I_busy (N64)
    LUT4:I2->O             1   0.549   1.035  I_wb_dat_o_0 (wb_dat_o_0_OBUF)
    OBUF:I->O                  4.668          wb_dat_o_0_OBUF (wb_dat_o_0)
    ----------------------------------------
    Total                     10.658ns (6.851ns logic, 3.807ns route)
                                       (64.3% logic, 35.7% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               9.098ns (Levels of Logic = 3)
  Source:            wb_adr_i_1
  Destination:       wb_dat_o_0

  Data Path: wb_adr_i_1 to wb_dat_o_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    IBUF:I->O             11   0.776   2.070  wb_adr_i_1_IBUF (wb_adr_i_1_IBUF)
    LUT4:I0->O             1   0.549   1.035  I_wb_dat_o_0 (wb_dat_o_0_OBUF)
    OBUF:I->O                  4.668          wb_dat_o_0_OBUF (wb_dat_o_0)
    ----------------------------------------
    Total                      9.098ns (5.993ns logic, 3.105ns route)
                                       (65.9% logic, 34.1% route)

=========================================================================
CPU : 9.22 / 9.67 s | Elapsed : 10.00 / 10.00 s
 
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