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[/] [miniuart2/] [trunk/] [sim/] [ModelSim/] [test_bench2/] [clk.in] - Rev 26

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-----------------------------
-- file clk.in
-----------------------------
--
-- build a clock signal at 10MHz
-- format : 
-- p -> period
-- d -> delay / start. simu. > 0
-- r -> cyclic ratio in %
-- or 
-- h high state time
-- c -> cycle number (~pattern number)
----------------------
p 100 ns
d 1 ns
r 50
c 50000000
--
-- end of file

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