OpenCores
URL https://opencores.org/ocsvn/miniuart2/miniuart2/trunk

Subversion Repositories miniuart2

[/] [miniuart2/] [trunk/] [sim/] [ModelSim/] [test_bench3/] [patt.in] - Rev 26

Compare with Previous | Blame | View Log

-----------------------------
-- file patt.IN
-----------------------------
-- clk 100 ns
--
-- time run 220 us
------------------------------------------ 
------------------------------------------
--     WB_RST_I => PATT(0),
--     WB_ADR_I => PATT(2 downto 1),
--     WB_DAT_I => PATT(10 downto 3),
--     WB_DAT_O => VISU(7 downto 0),
--     WB_WE_I  => PATT(11),
--     WB_STB_I => PATT(12),
--     WB_ACK_O => VISU(8),
--   
--     IntTx_O  => VISU(9),
--     IntRx_O  => VISU(10),
--
--     TxD_PAD_O => VISU(11),
--     RxD_PAD_I => PATT(13)
--
A     0 ns b_1_00_00000000_00_1  --rst async
R 17.36 us b_0_00_00000000_00_0  --start bit
R 17.36 us b_0_00_00000000_00_0  --bit 0   |
R 17.36 us b_1_00_00000000_00_0  --bit 1   |
R 17.36 us b_0_00_00000000_00_0  --bit 2   |
R 17.36 us b_0_00_00000000_00_0  --bit 3   } byte 0x32
R 17.36 us b_1_00_00000000_00_0  --bit 4   |
R 17.36 us b_1_00_00000000_00_0  --bit 5   |
R 17.36 us b_0_00_00000000_00_0  --bit 6   |
R 17.36 us b_0_00_00000000_00_0  --bit 7   |
R 17.36 us b_1_00_00000000_00_0  --stop bit
A 190   us b_1_10_00000000_01_0  --read status register
R 100   ns b_1_00_00000000_00_0  --release strobe
A 200   us b_1_10_00000000_00_0  --read Rx register
R 100   ns b_1_00_00000000_00_0  --release strobe
--
-- end file

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.