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[/] [minsoc/] [branches/] [rc-1.0/] [prj/] [src/] [adbg_top.prj] - Rev 160

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PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
PROJECT_SRC=(adbg_wb_biu.v
adbg_wb_module.v
adbg_or1k_module.v
adbg_wb_defines.v
adbg_defines.v
adbg_crc32.v
adbg_or1k_biu.v
adbg_or1k_defines.v
adbg_or1k_status_reg.v
adbg_top.v)

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