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[/] [minsoc/] [branches/] [rc-1.0/] [prj/] [src/] [altera_virtual_jtag.prj] - Rev 115
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PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/altera_virtual_jtag/rtl/vhdl/
PROJECT_SRC=altera_virtual_jtag.vhd
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