Subversion Repositories minsoc

PROJECT_DIR=(backend bench/verilog bench/verilog/vpi bench/verilog/sim_lib rtl/verilog rtl/verilog/minsoc_startup)
PROJECT_SRC=(minsoc_defines.v
minsoc_bench_defines.v
minsoc_bench.v
minsoc_memory_model.v
dbg_comm_vpi.v
fpga_memory_primitives.v
timescale.v
minsoc_top.v
spi_top.v
spi_defines.v
spi_shift.v
spi_clgen.v
OR1K_startup_generic.v
minsoc_tc_top.v
minsoc_onchip_ram.v
minsoc_clock_manager.v
minsoc_onchip_ram_top.v)