OpenCores

URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [prj/] [src/] [uart_top.prj] - Rev 171

Go to most recent revision | Compare with Previous | Blame | View Log

PROJECT_DIR=rtl/verilog/uart16550/rtl/verilog
PROJECT_SRC=(uart_top.v
uart_sync_flops.v
uart_transmitter.v
uart_debug_if.v
uart_wb.v
uart_receiver.v
uart_tfifo.v
uart_regs.v
uart_rfifo.v
uart_defines.v
raminfr.v)

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.