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[/] [minsoc/] [branches/] [rc-1.0/] [prj/] [src/] [uart_top.prj] - Rev 173

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PROJECT_DIR=rtl/verilog/uart16550/rtl/verilog
PROJECT_SRC=(uart_top.v
uart_sync_flops.v
uart_transmitter.v
uart_debug_if.v
uart_wb.v
uart_receiver.v
uart_tfifo.v
uart_regs.v
uart_rfifo.v
uart_defines.v
raminfr.v)

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